EP-4736234-A1 - TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY

Abstract

Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

Inventors

• GAIDE, BRIAN C.
• DATE, SNEHA BHALCHANDRA
• NOGUERA SERRA, JUAN J.

Assignees

• Xilinx, Inc.

Dates

Publication Date

20260506

Application Date

20240617

Claims (15)

1. 1 . A three-dimensional (3D) die stack, comprising: a programmable logic (PL) die comprising a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die; and a compute die stacked on top of the PL die, the compute die comprising a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die, wherein the three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.
2. 2. The 3D die stack of claim 1 , wherein each data processing engine included in the plurality of data processing engines is associated with same number of configurable blocks included in the plurality of configurable blocks.
3. 3. The 3D die stack of any of claims 1 or 2, wherein the second electrical connections of each data processing engine included in the plurality of data processing engines are electrically connected, at a die-to-die interface between the PL die and the compute die, to the first electrical connections of the same number of configurable blocks included in the plurality of configurable blocks.
4. 4. The 3D die stack of any of claims 1-3, wherein each configurable block included in the plurality of configurable blocks comprises a programmable interconnect, and each data processing engine included in the plurality of data processing engines is electronically connected to substantially the same number of programmable interconnects included in the plurality of configurable blocks.
5. 5. The 3D die stack of any of claims 1-4, wherein each data processing engine included in the plurality of data processing engines is directly coupled to substantially the same number of programmable interconnects included in the plurality of configurable blocks.
6. 6. The 3D die stack of any of claims 1-5, wherein each configurable block included in the plurality of configurable blocks comprises a configurable logic element, and each data processing engine included in the plurality of data processing engines is associated with substantially the same number of configurable logic elements included in the plurality of configurable blocks.
7. 7. The 3D die stack of any of claims 1-6, wherein the PL die comprises a field- programmable gate array (FPGA) fabric including the plurality of configurable blocks.
8. 8. The 3D die stack of any of claims 1 -7, wherein the plurality of first electrical connections are hybrid oxide bonded to the plurality of second electrical connections.
9. 9. The 3D die stack of any of claims 1-8, wherein the plurality of first electrical connections and the plurality of second electrical connections have a pitch of less than 5 microns.
10. 10. The 3D die stack of any of claims 1 -9, wherein the plurality of second electrical connections comprise through-silicon vias (TSVs).
11. 11. A computing system, comprising: a memory; and a three-dimensional (3D) die stack coupled to the memory and comprising: a programmable logic (PL) die comprising a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die; and a compute die stacked on top of the PL die, the compute die comprising a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die, wherein the three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and A/ data processing engines included in the plurality of data processing engines.
12. 12. The computing system of claim 11 , wherein each data processing engine included in the plurality of data processing engines is associated with same number of configurable blocks included in the plurality of configurable blocks.
13. 13. The computing system of claims 11 or 12, wherein the second electrical connections of each data processing engine included in the plurality of data processing engines are electrically connected, at a die-to-die interface between the PL die and the compute die, to the first electrical connections of the same number of configurable blocks included in the plurality of configurable blocks.
14. 14. The computing system of any of claims 11 -13, wherein each configurable block included in the plurality of configurable blocks comprises a programmable interconnect, and each data processing engine included in the plurality of data processing engines is electronically connected to substantially the same number of programmable interconnects included in the plurality of configurable blocks.
15. 15. The computing system of any of claims 11 -14, wherein the plurality of first electrical connections and the plurality of second electrical connections have a pitch of less than 5 microns.

Description

TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY TECHNICAL FIELD [0001] Examples of the present disclosure generally relate to integrated circuit (IC) devices, and more specifically, to a tiled compute and programmable logic array. BACKGROUND [0002] Increasingly, high-performance computing systems implement large numbers of data processing engines and programmable logic (PL) (e.g.< a field- programmable gate array or “FPGA”) within the same die and/or integrated circuit (IC) package. Such systems generally provide a flexible and highly parallel computing interface that can be adapted to a wide variety of applications. However, the architectures implemented in current systems suffer from a number of drawbacks. [0003] For example, such systems commonly implement network-based communications in which data processing engines communicate with programmable logic and other IC components via an edge interface. One drawback of this configuration is that, as more and more processing elements need to communicate through an edge interface, the routing channels associated with the edge interface become saturated. As the routing channels approach saturation, routing congestion increases, limiting bandwidth and/or increasing latency between data processing engines and programmable logic. Additionally, due to routing congestion, data processing engines and programmable logic positioned far away from an edge of the interface may have difficulty meeting timing closure requirements, effectively limiting the total number of resources that can be utilized for a given process. SUMMARY [0004] Techniques for implementing a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and /V data processing engines included in the plurality of data processing engines. [0005] One example described herein is a computing system. The computing system inciudes a memory and a three-dimensional (3D) die stack coupled to the memory. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three- dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines. BRIEF DESCRIPTION OF DRAWINGS [0006] So that the manner in which the above recited features can be understood in detail, a more particular description, briefly summarized above, may be had by reference to example implementations, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical example implementations and are therefore not to be considered limiting of its scope. [0007] Fig. 1 is a block diagram of a SoC that includes a data processing engine array and programmable logic, according to an example. [0008] Fig. 2 is a block diagram of a data processing engine in the data processing engine array, according to an example. [0009] Fig. 3 illustrates a field programmable gate array (FPGA) implementation of a programmable logic (PL) die, according to an example [0010] Fig. 4A illustrates a schematic elevation view of a compute die and PL die, according to an example. [0011] Fig. 4B illustrates a schematic elevation view of a three-dimensional (3D) die stack that includes compute die and PL die, according to an example. [0012] Fig. 5 illustrates input and output connections formed in the z-direction between programmable interconnect elements included in the PL die and a data processing engine and/or interconnect included in compute die, according to an example. [0013] Fig. 6A illustrates a schematic elevation view of a compute die and PL die, according to an example. [0014] Fig. 68 illustrates a schematic elevation view of a three-dimensional (3D) die stack in which an interconnect included in compute die does not vertically align with programmable interconnect elements included in PL die, according to an example. [0015] Fig. 7 illustrates metal tracks fabricated between z-interface cells included in compute die and an interconnect included in the PL die, according to an example. [0016] F igs. 8A-8C illustrate techniques f