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EP-4736241-A1 - PHOTONIC INTEGRATED CIRCUIT WITHIN A CAVITY OF INTERPOSER

EP4736241A1EP 4736241 A1EP4736241 A1EP 4736241A1EP-4736241-A1

Abstract

An apparatus comprising an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (PIC).

Inventors

  • LI, Xiaoqian
  • JAYARAM, VIDYA
  • MAHAJAN, RAVINDRANATH
  • JAYARAMAN, SAIKUMAR

Assignees

  • INTEL Corporation

Dates

Publication Date
20260506
Application Date
20231116

Claims (20)

  1. 1. An apparatus comprising: an interposer comprising: first conductive contacts on a top surface of the interposer, second conductive contacts on a bottom surface of the interposer, and third conductive contacts on a surface of a cavity of the interposer; first vias coupling a first portion of the second conductive contacts to the first conductive contacts; and second vias coupling a second portion of the second conductive contacts to the third conductive contacts; and a photonics integrated circuit (PIC) within the cavity of the interposer and coupled to the third conductive contacts.
  2. 2. The apparatus of claim 1, wherein the interposer comprises a substrate comprising silicon.
  3. 3. The apparatus of claim 1, wherein the interposer comprises a substrate comprising glass.
  4. 4. The apparatus of any of claims 1-3, wherein the PIC comprises an active region proximate a first surface of the PIC, the active region to communicate an optical signal.
  5. 5. The apparatus of claim 4, wherein the first surface of the PIC is oriented facing down towards the surface of the cavity.
  6. 6. The apparatus of claim 4, wherein the first surface of the PIC is oriented facing up away from the surface of the cavity.
  7. 7. The apparatus of any of claims 1-3, further comprising a light source within the cavity of the interposer.
  8. 8. The apparatus of claim 7, wherein the light source comprises a microLED array.
  9. 9. The apparatus of claim 8, further comprising a plurality of microlenses on microLEDs of the microLED array.
  10. 10. The apparatus of claim 8, further comprising glass between the microLED array and an active region of the PIC, the glass comprising at least one waveguide.
  11. 11. The apparatus of claim 8, wherein the interposer further comprises a mirror to change a path of an optical signal from lateral to vertical, and wherein a coupler is attached to the top surface or the bottom surface of the interposer.
  12. 12. The apparatus of claim 7, wherein the light source comprises a laser.
  13. 13. The apparatus of any of claims 1-3, further comprising: a coupler attached to the interposer; and a waveguide of the interposer, the waveguide to communicate the optical signal between an active region of the PIC and the coupler.
  14. 14. A system comprising: a package to couple to a printed circuit board, the package comprising: a substrate; an integrated circuit device; an interposer between at least a portion of the substrate and at least a portion of the integrated circuit device; and a photonics integrated circuit (PIC) within a cavity of the interposer.
  15. 15. The system of claim 14, wherein the package further comprises a second integrated circuit coupled to the substrate.
  16. 16. The system of claim 14, further comprising the printed circuit board.
  17. 17. The system of any of claims 14-16, wherein the package further comprises a plurality of PICs within a plurality of cavities of the interposer.
  18. 18. An apparatu s com pri si ng : an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (PIC).
  19. 19. The apparatus of claim 18, further comprising the PIC, wherein the PIC is disposed within the cavity.
  20. 20. The apparatus of any of claims 18-19, wherein the interposer comprises first vias of a first length to couple to the conductive contacts of the integrated circuit device and second vias of a second length to couple to the conductive contacts of the PIC, wherein the second length is shorter than the first length.

Description

PHOTONIC INTEGRATED CIRCUIT WITHIN A CAVITY OF INTERPOSER CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority to U.S. Patent Application Serial No. 18/346,116 filed on June 30, 2023, and entitled “PHOTONIC INTEGRATED CIRCUIT WITHIN A CAVITY OF INTERPOSER”, which is hereby incorporated by reference in its entirety. BACKGROUND [0002] A photonic integrated circuit (PIC), sometimes referred to as an integrated optical circuit, is an integrated circuit device that incorporates multiple photonic components to create a functional circuit. For example, a PIC may be capable of detecting, generating, transporting, and/or processing light. Unlike electronic integrated circuits (EICs) that rely on electrons, photonic integrated circuits may utilize particles of light called photons. A PIC may enable the manipulation of information signals carried by optical wavelengths, typically within the visible spectrum or near infrared range. BRIEF DESCRIPTION OF THE DRAWINGS [0003] FIG. 1 illustrates example phases of manufacture of an example downward facing PIC within a cavity of an EIC interposer with a silicon substrate. [0004] FIG. 2 illustrates example phases of manufacture of an example downward facing PIC within a cavity of an interposer with a glass substrate. [0005] FIG. 3 illustrates an example upward facing PIC within a cavity of an interposer with a glass substrate. [0006] FIG. 4 illustrates an example PIC and integrated light source within a cavity of an interposer with a glass substrate. [0007] FIG. 5 illustrates another example PIC and integrated light source within a cavity of an interposer with a glass substrate. [0008] FIG. 6 illustrates an example integrated light source and upward facing PIC within a cavity of an interposer with a glass substrate. [0009] FIGs. 7A-7D illustrate example package level integrations for a PIC within a cavity of an interposer. [0010] FIG. 8 illustrates multiple PICs in cavities of an example interposer. [0011] FIG. 9 illustrates multiple PICs in cavities of an example interposer with a glass substrate. [0012] FIG. 10 illustrates an example process for forming a PIC within a cavity of an interposer. [0013] FIG. 11 is a top view of a wafer and dies. [0014] FIG. 12 is a cross-sectional side view of an integrated circuit device. [0015] FIG. 13 is a cross-sectional side view of an integrated circuit device assembly. [0016] FIG. 14 is a block diagram of an example electrical device. DETAILED DESCRIPTION [0017] Off-package input/output (VO) bandwidth has been steadily increasing, approximately doubling every two years. Accordingly, an emphasis has been placed on scaling packaging and I/O technologies to meet this bandwidth demand. As a result, package pin counts and I/O data rates continue to increase. However, the electrical VO reach (e.g., the length of electrical printed circuit board (PCB) trace or cable) reduces at increased date rates. Additionally, VO energy efficiency improvement has drastically slowed, leading to a quickly approaching I/O power wall for high-performance packages. Co-package optics solutions have been showing benefit for both power efficiency and bandwidth improvement. [0018] There are several architecture options for co-package optics. For example, a monolithic photonic integrated circuit (PIC) or a PIC -electronic integrated circuit (EIC) stack may be attached to an organic substrate or the PIC may be placed in a cavity of an organic substrate and the EIC may be placed above the PIC. Optical coupling from the PIC to the external world may be implemented through fiber pigtails or fiber array units, but such solutions may have yield and handling (e.g., in both assembly and system integration) challenges for packaging and system integration. [0019] In various embodiments of the present disclosure, a PIC is placed within an open cavity of an interposer. For example, the PIC may be placed within a cavity of an interposer comprising a glass or silicon substrate. In some examples, the interposer may include an integrated light (e.g., laser) source within the cavity or an additional cavity of the interposer or may utilize an external light source (e.g., a light source not connected to the interposer, but included within a component or IC device coupled to the interposer). [0020] Various embodiments described herein may result in one or more technical advantages, such as improved optical coupling, improved yield, reduced warpage or stress impact on the PIC, and/or improved system architecture compatibility. [0021] In some embodiments, yield may be improved. Edge coupling may typically be accomplished through a fiber array unit (FAU) attached to a PIC. However, if the attachment of the FAU to the PIC is not successful, the PIC and the package including the PIC may have to be sacrificed. In some embodiments, pigtails/FAUs are not connected to the PIC and thus wastage of known good PICs may be avoided. [0022] FIG. 1 illustrates example phases