EP-4736305-A1 - PULSE FREQUENCY MODULATION (PFM) MODE FOR A MULTIPHASE CONVERTER

Abstract

A circuit (100) includes a plurality of control logic circuits (108a-108n), each of the control logic circuits configured to provide respective pulses at different time periods. The circuit (100) further includes a timer circuit (116) configured to provide a timer signal to each of the control logic circuits (108a-108n) based on an output voltage, wherein the timer signal determines a frequency of the respective pulses. Furthermore, the circuit (100) includes a rotator circuit (128) configured to provide a plurality of rotator signals to the control logic circuits (108a-108n), respectively, wherein each control logic circuit is configured to determine a time period of the different time periods during which to generate the respective pulses based on the respective rotator signal.

Inventors

• PAHKALA, Janne
• VAANANEN, ARI

Assignees

• Texas Instruments Incorporated

Dates

Publication Date

20260506

Application Date

20240614

Claims (20)

1. 1. A circuit comprising: a plurality of control logic circuits, wherein each of the control logic circuits is configured to provide respective pulses at different time periods; a timer circuit configured to provide a timer signal to each of the control logic circuits based on an output voltage, wherein the timer signal determines a frequency of the respective pulses; and a rotator circuit configured to provide a plurality of rotator signals to the control logic circuits, respectively, wherein each control logic circuit is configured to determine a time period of the different time periods during which to generate the respective pulses based on the respective rotator signal.
2. 2. The circuit of claim 1, wherein each of the control logic circuits is configured to provide the respective pulses during the respective time period based on the timer signal and the respective rotator signal.
3. 3. The circuit of claim 2, wherein the timer signal has a triggered state and a reset state, and a respective control logic circuit is configured to start generating the respective pulses when the timer signal transitions to the triggered state and the respective rotator signal is active.
4. 4. The circuit of claim 3, wherein the timer circuit is configured to generate the timer signal based on a comparison of a voltage ramp signal and a timer reference voltage.
5. 5. The circuit of claim 4, wherein the timer signal is transitioned to the triggered state when the voltage ramp signal is greater than the timer reference voltage, and the timer signal is transitioned to the reset state when the voltage ramp signal is less than the timer reference voltage.
6. 6. The circuit of claim 4, wherein the voltage ramp signal is generated based on a voltage control signal indicative of the output voltage and a reset signal.
7. 7. The circuit of claim 6, wherein, when one of the control logic circuits starts generating pulses, the reset signal modifies the voltage ramp signal to transition the timer signal to the reset state.
8. 8. The circuit of claim 7, further comprising a reset signal generation circuit configured to generate the reset signal such that the reset signal is set to a logic high state when any one of the control logic circuits starts generating pulses.
9. 9. The circuit of claim 8, wherein each of the control logic circuit is configured to provide a corresponding pulse generation indication signal to the reset signal generation circuit, wherein the pulse generation indication signal provides an indication that the corresponding control logic circuit has started generating pulses.
10. 10. The circuit of claim 6, further comprising a voltage compensation circuit configured to generate the voltage control signal based on a comparison of a feedback voltage indicative of the output voltage and an output reference voltage.
11. 11. The circuit of claim 1, wherein the rotator circuit is configured to generate the plurality of rotator signals based on the timer signal.
12. 12. A circuit comprising: a first control logic circuit having a first input, a second input, and an output; a second control logic circuit having a first input, a second input, and an output; a timer circuit having an input and an output, the output coupled to the first input of the first control logic circuit and to the first input of the second control logic circuit, and the input of the timer circuit adapted to be coupled to an output terminal; and a rotator circuit having an input, a first output and a second output, the input coupled to the output of the timer circuit, the first output coupled to the second input of the first control logic circuit and the second output coupled to the second input of the second control logic circuit.
13. 13. The circuit of claim 12, wherein the first control logic circuit is configured to provide a first set of pulses at the corresponding output and the second control logic circuit is configured to provide a second set of pulses at the corresponding output, during different time periods, based on a timer signal at the first input of the first control logic circuit and the second control logic circuit.
14. 14. The circuit of claim 13, further comprising a first current sense comparator circuit coupled to the first control logic circuit and a second current sense comparator circuit coupled to the second control logic circuit, each of the first current sense comparator circuit and the second current sense comparator circuit including a respective peak current comparator circuit configured to generate a respective peak current control signal and a respective valley current comparator circuit configured to generate a respective valley current control signal, based on a respective output current.
15. 15. The circuit of claim 14, wherein the first control logic circuit is configured to provide the first set of pulses further based on the peak current control signal and the valley current control signal from the first current sense comparator circuit and the second control logic circuit is configured to provide the second set of pulses further based on the peak current control signal and the valley current control signal from the second current sense comparator circuit.
16. 16. The circuit of claim 15, wherein the first control logic circuit and the second control logic circuit are configured to generate the first set of pulses and the second set of pulses, respectively, during a PFM mode and wherein the first control logic circuit and the second control logic circuit are configured to generate respective pulse width modulation (PWM) pulses based on the peak current control signal and the valley current control signal during a PWM mode.
17. 17. The circuit of claim 16, wherein, during the PFM mode, the first current sense comparator circuit is enabled only during a time period when the first control logic circuit is generating a pulse, and the second current sense comparator circuit is enabled only during a time period when the second control logic circuit is generating a pulse.
18. 18. A system comprising: a plurality of power converter circuits, wherein an output terminal of each of the power converter circuits is coupled to a common output terminal; a plurality of control logic circuits each configured to provide respective pulses to a respective one of the power converter circuits at different time periods; a timer circuit configured to provide a timer signal to each respective one of the control logic circuits, the timer signal being based on an amplitude of an output voltage at the common output terminal of the power converter circuits, wherein the timer signal determines a frequency of the respective pulses; and a rotator circuit configured to provide one of a plurality of rotator signals to each respective one of the control logic circuits, wherein each of the rotator signals determines a time period of the different time periods during which the corresponding control logic circuit generates the respective pulses.
19. 19. The system of claim 18, wherein each of the control logic circuits is configured to generate the respective pulses during the respective time period based on the timer signal and the respective rotator signal.
20. 20. The system of claim 19, wherein the timer signal has a triggered state and a reset state, and a respective control logic circuit is configured to start generating the respective pulses when the timer signal transitions to the triggered state and the respective rotator signal is active.

Description

PULSE FREQUENCY MODULATION (PFM) MODE FOR A MULTIPHASE CONVERTER [0001] This description relates to current mode multiphase power converters, in particular, to a system that facilitates a rotation pulse frequency modulation (PFM) mode in current mode multiphase power converters. BACKGROUND [0002] Power converters are a family of electrical circuits which convert electrical energy from one level of voltage/current/frequency to another using semiconductor-based electronic switches. A characteristic of these types of circuits is that the switches are operated only in one of two states either fully ON or fully OFF - unlike other types of electrical circuits where the control elements are operated in a (near) linear active region. Multiphase power converters include a parallel set of power electronic stages or phases, each stage having corresponding switch components. Each of the power electronic stages or phases are coupled to a common output terminal. Multiphase operation gives flexibility for powering various loads as the phases can be configured to operate in parallel or as stand-along configuration. Further, the multiphase power converters provide scalable output current and reduces output current ripple. [0003] Multiphase power converters are operated in both pulse width modulation (PWM) mode and pulse frequency modulation (PFM) mode. In some examples, the multiphase power converters transition from the PWM mode to the PFM mode during light load conditions. Multiphase power converters, which are used to power automotive processors, are required to operate with minimized output capacitance due to cost sensitive market. The multiphase power converters are also required to have a low power mode with good efficiency to ensure battery life. SUMMARY [0004] An example circuit includes a plurality of control logic circuits, each of the control logic circuits configured to provide respective pulses at different time periods. The circuit further includes a timer circuit configured to provide a timer signal to each of the control logic circuits based on an output voltage, wherein the timer signal determines a frequency of the respective pulses. Furthermore, the circuit includes a rotator circuit configured to provide a plurality of rotator signals to the control logic circuits, respectively, wherein each control logic circuit is configured to determine a time period of the different time periods during which to generate the respective pulses based on the respective rotator signal. [0005] Another example circuit includes a first control logic circuit having a first input, a second input, and an output; and a second control logic circuit having a first input, a second input, and an output. The circuit further includes a timer circuit having an input and an output, the output coupled to the first input of the first control logic circuit and to the first input of the second control logic circuit, and the input of the timer circuit adapted to be coupled to a common output terminal. Furthermore, the circuit includes a rotator circuit having an input, a first output and a second output, the input coupled to the output of the timer circuit, the first output coupled to the second input of the first control logic circuit and the second output coupled to the second input of the second control logic circuit. [0006] A yet another example includes a system that includes a plurality of converter circuits, wherein an output terminal of each of the converter circuits is coupled to a common output terminal; and a plurality of control logic circuits each configured to provide respective pulse frequency modulation (PFM) pulses to a respective one of the converter circuits at different time periods. The system further includes a pulse frequency modulation (PFM) timer circuit configured to provide a timer signal to each respective one of the control logic circuits, the timer signal being based on an amplitude of an output voltage at the common output terminal of the converter circuits, wherein the timer signal determines a frequency of the respective pulses. Furthermore, the system includes a rotator circuit configured to provide one of a plurality of rotator signals to each respective one of the control logic circuits, wherein each of the rotator signals determines a time period of the different time periods during which the corresponding control logic circuit generates the respective pulses. BRIEF DESCRIPTION OF THE DRAWINGS [0007] FIG. 1 illustrates a simplified block diagram of an example multiphase power converter system. [0008] FIG. 2 illustrates an example implementation of a multiphase power converter system. [0009] FIG. 3 illustrates an example implementation of a PFM timer circuit. [0010] FIG. 4 illustrates an example implementation of a control logic circuit. [0011] FIG. 5 illustrates another example implementation of a control logic circuit. [0012] FIG. 6 illustrates a graph that depicts various plots associated with a mul