EP-4736319-A1 - AMPLIFIER SYSTEM WITH OUTPUT STAGE

Abstract

In at least one embodiment, an amplifier (180) is provided. The amplifier (180) includes an input stage, a plurality of output stages, and a combining stage (106). The input stage includes a first input transistor and a second input transistor to receive an input signal. Each output stage includes at least one output resistor. The plurality of output stages is configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load. The combining stage (106) includes a plurality of combining resistors, each combining resistor forming a star connection with the output resistors for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load.

Inventors

• DANYUK, Dimitri
• SHIMIAEI, Danial

Assignees

• Harman International Industries, Incorporated

Dates

Publication Date

20260506

Application Date

20230630

Claims (20)

1. 1. An amplifier comprising: an input stage including a first input transistor and a second input transistor to receive an input signal; a plurality of output stages, each output stage includes a plurality of output resistors, the plurality of output stages being configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load; and a combining stage including a plurality of combining resistors, each combining resistor forming a star connection with the plurality of output resistors for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load.
2. 2. The amplifier of claim 1, wherein each of the plurality of output stages includes a first output transistor and a second output transistor, the first output transistor and the second output transistor each having an emitter that is coupled to at least one of the plurality of output resistors.
3. 3. The amplifier of claim 1, wherein each of the plurality of output stages includes a first output transistor, a second output transistor, a first output resistor, and a second output resistor, and wherein the first output transistor includes an emitter that is coupled to the first output resistor and the second output transistor includes an emitter that is coupled to the second output resistor.
4. 4. The amplifier of claim 3, wherein a resistance of the first output resistor is similar to a resistance of the second output resistor.
5. 5. The amplifier of claim 3, wherein the first output transistor and the first output resistor provide the first voltage to the at least one combining resistor in the push mode.
6. 6. The amplifier of claim 3, wherein the second output transistor and the second output resistor are configured to receive a second voltage from the at least one combining resistor in the pull mode.
7. 7. The amplifier of claim 3, wherein a sum of a resistance of the first output resistor and a first combining resistor of the combining stage is similar to a sum of a resistance of the second output resistor and a second combining resistor to enable the load to receive the low distortion output signal.
8. 8. An amplifier comprising: an input stage including a first input transistor and a second input transistor to receive an input signal; a plurality of output stages, each output stage includes at least one current setting resistor, the plurality of output stages being configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load; and a combining stage including a plurality of combining resistors, each combining resistor being positioned in series each output stage, respectively, and forming a delta connection with a corresponding current setting resistor to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load.
9. 9. The amplifier of claim 8, wherein each of the plurality of output stages includes a first output transistor, a second output transistor, and at least one output resistor, and wherein the first output transistor and the second output transistor each include an emitter that is coupled to the at least one output resistor.
10. 10. The amplifier of claim 8, wherein each of the plurality of output stages includes a first output transistor, a second output transistor, a first output resistor and a second output resistor, and wherein the first output transistor includes an emitter that is coupled to the first output resistor and the second output transistor includes an emitter that is coupled to the second output resistor.
11. 11. The amplifier of claim 10, wherein a resistance of the first output resistor is similar to a resistance of the second output resistor.
12. 12. The amplifier of claim 10, wherein the first output transistor and the first output resistor provide the first voltage to the at least one combining resistor in the push mode.
13. 13. The amplifier of claim 10, wherein the second output transistor and the second output resistor are configured to receive a second voltage from the at least one combining resistor in the pull mode.
14. 14. The amplifier of claim 8, wherein a sum of a resistance of a first output resistor of at least one of the plurality of output stages and a resistance of a first combining resistor of the combining stage is similar to a sum of a resistance of a second output resistor of the at least one of the plurality of output stages and resistance of a second output resistor of a second combining resistor to enable the load to receive the low distortion output signal.
15. 15. The amplifier of claim 8 is one of a class A, class B, and class AB amplifier.
16. 16. An amplifier comprising: a plurality of output stages, each output stage includes at least one output resistor, the plurality of output stages being configured to operate in a one of a push mode to output a positive cycle of an input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load; and a combining stage including a plurality of combining resistors, each combining resistor forming a star connection with the at least one output resistor for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load.
17. 17. The amplifier of claim 16, wherein each of the plurality of output stages includes a first output transistor and a second output transistor, the first output transistor and the second output transistor each having an emitter that is coupled to the at least one output resistor.
18. 18. The amplifier of claim 16, wherein each of the plurality of output stages includes a first output transistor, a second output transistor, a first output resistor, and a second output resistor, and wherein the first output transistor includes an emitter that is coupled to the first output resistor and the second output transistor includes an emitter that is coupled to the second output resistor.
19. 19. The amplifier of claim 18, wherein a resistance of the first output resistor is similar to a resistance of the second output resistor.
20. 20. The amplifier of claim 16, wherein a sum of a resistance of a first output resistor of at least one of the plurality of output stages and a resistance of a first combining resistor of the combining stage is similar to a sum of a resistance of a second output resistor of the at least one of the plurality of output stages and resistance of a second output resistor of a second combining resistor to enable the load to receive the low distortion output signal.

Description

AMPLIFIER SYSTEM WITH OUTPUT STAGE TECHNICAL FIELD [0001] Aspects disclosed herein generally relate to an amplifier system having output stage. These aspects and others will be discussed in more detail below. BACKGROUND [0002] Class AB amplifiers generally combine Class A and Class B amplifiers to provide an amplifier having more efficiency than the Class A amplifier but with lower distortion than a Class B amplifier. This may be achieved by biasing transistors so that such transistors conduct when the output signal is close to zero (e.g., the point where Class B amplifiers introduce non-linearities). [0003] For smaller signals, both transistors of the Class AB amplifier are active thereby behaving as a Class A amplifier. For larger signal excursions, one transistor may be active for each half of a waveform thereby acting like a Class B amplifier. SUMMARY [0004] In at least one embodiment, an amplifier is provided. The amplifier includes an input stage, a plurality of output stages, and a combining stage. The input stage includes a first input transistor and a second input transistor to receive an input signal. Each output stage includes at least one output resistor. The plurality of output stages is configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load. The combining stage includes a plurality of combining resistors, each combining resistor forming a star connection with the output resistors for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load. [0005] In at least another embodiment, an amplifier is provided. The amplifier includes an input stage, a plurality of output stages, and a combining stage. The input stage includes a first input transistor and a second input transistor to receive an input signal. Each output stage includes at least one current setting resistor, the plurality of output stages being configured to operate in a one of a push mode to output a positive cycle of the input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load. The combining stage includes a plurality of combining resistors, each combining resistor being positioned in series each output stage, respectively, and forming a delta connection with a corresponding current setting resistor to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load. [0006] In at least another embodiment, an amplifier is provided. The amplifier includes a plurality of output stages and a combining stage. Each output stage includes at least one output resistor, the plurality of output stages being configured to operate in a one of a push mode to output a positive cycle of an input signal to a load and a pull mode to absorb a negative cycle of the input signal from the load. The combining stage includes a plurality of combining resistors, each combining resistor forming a star connection with the at least one output resistor for each output stage to receive a first voltage therefrom and to generate an output voltage based on the first voltage to produce a low distortion output signal at the load. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The embodiments of the present disclosure are pointed out with particularity in the appended claims. However, other features of the various embodiments will become more apparent and will be best understood by referring to the following detailed description in conjunction with the accompany drawings in which: [0008] FIGURE 1 depicts one example of an amplifier; [0009] FIGURE 2 depicts one example of plot showing an incremental gain associated with a different bias setting for the amplifier of FIGURE 1; [0010] FIGURE 3 depicts one example of a plot showing an individual harmonic distortion as a function of an output voltage for an overbiased push-pull output stage of the amplifier of FIGURE 1; [0011] FIGURE 4 depicts an amplifier in accordance with one embodiment of the present disclosure; [0012] FIGURE 5A and 5B depict a simulation of an incremental gain with different bias setting for individual push-pull complementary pairs and an output stage as a whole in accordance with one embodiment; [0013] FIGURE 6 depicts one example of a plot showing an individual harmonic distortion as a function of an output voltage for an overbiased push-pull output stage of the amplifier of FIGURE 4; [0014] FIGURE 7 depicts an amplifier in accordance with one embodiment of the present disclosure; and [0015] FIGURE 8 depict simplified gain plots that illustrate characteristics for the disclosed amplifiers of FIGURES 4 and 7 in accordance with one embodiment of the present disclosure. DETAILED DESCRIPTION [0016] As required, detailed embodiments of the present inve