EP-4736320-A1 - LOW NOISE AMPLIFIER WITH POST DISTORTION CIRCUIT

Abstract

An exemplary RF amplifier circuit has a LNA (110) with its output coupling RF signals to a load (130). A post distortion (PD) circuit having a semiconductor device (205) with a control gate biased to cause the semiconductor device (205) to operate in a nonlinear region at or near pinch-off that is coupled to the output of the LNA (110). The PD circuit generates at least one PD intermodulation product at the PD port in response to the RF signals being received from the LNA (110) through the coupling. The at least one PD intermodulation product combining with the intermodulation product produced by the LNA (110) to cause a reduction of the intermodulation product at the load by at least several dB for at least one frequency in the range of frequencies.

Inventors

• Ghanevati, Manouchehr
• LEONG, Kevin, M.
• SIDDIQUI, MANSOOR, K.

Assignees

• Northrop Grumman Systems Corporation

Dates

Publication Date

20260506

Application Date

20240614

Claims (20)

1. 1. An RF amplifier circuit operating within a range of frequencies comprising: a low noise amplifier producing RF signals on an output; a load coupled to the output to receive the RF signals; a post distortion (PD) circuit having a semiconductor device with a control gate biased to cause the semiconductor device to operate in a nonlinear region at or near pinch-off; the PD circuit having a PD port that is coupled to the output of the low noise amplifier; the PD circuit generating at least one PD intermodulation product at the PD port in response to the RF signals being received from the low noise amplifier through the coupling by the PD circuit, the at least one PD intermodulation product being out of phase to an intermodulation product produced by the low noise amplifier that is present at the output; the at least one PD intermodulation product combining with the intermodulation product produced by the low noise amplifier to cause a reduction of the intermodulation product at the load by at least 10 dB for at least one frequency in the range of frequencies.
2. 2 The RF amplifier circuit of claim 1 further comprising the PD circuit being coupled to the low noise amplifier only by an AC coupling so that no DC power used by the low noise circuit is utilized by the PD circuit.
3. 3. The RF amplifier circuit of claim 1 wherein the at least one PD intermodulation product and the intermodulation product produced by the low noise amplifier are each second order intermodulation products.
4. 4. The RF amplifier circuit of claim 1 further comprising a DC bias circuit, coupled to the control gate of the active semiconductor device of the PD circuit, provides a biasing voltage that establishes a DC quiescent point at or near pinch-off of the active semiconductor device.
5. 5. The RF amplifier circuit of claim 1 wherein active devices in the low noise amplifier and the semiconductor device are high electron mobility transistors (HEMT) having indium arsenide composite channel (IACC) technology.
6. 6. The RF amplifier circuit of claim 1 further comprising a resistor in series between the PD port and the output of the low noise amplifier, where a value of the resistor determines an amount of coupling between the PD circuit and the output of the low noise amplifier.
7. 7. The RF amplifier circuit of claim 1 further comprising at least one of an inductor and a capacitor connected between the PD port and the output of the low noise amplifier, where a value of the at least one inductor and capacitor contributes to determining a frequency with the range of frequencies where a maximum reduction of the intermodulation product at the load occurs.
8. 8. The RF amplifier circuit of claim 1 further comprising an inductor and a capacitor connected between the PD port and the output of the low noise amplifier, where values of the inductor and capacitor contributes to determining a frequency with the range of frequencies where a maximum reduction of the intermodulation product at the load occurs.
9. 9. The RF amplifier circuit of claim 1 wherein the low noise amplifier comprises: first and second transistors operating as a dual gate device; a bias circuit coupled to the first and second transistors establishes a DC quiescent voltage across each of the first and second transistors with the sum of the DC quiescent voltages across the first and second transistors being a total voltage; the bias circuit causing the DC quiescent voltage across the first transistor to be 30% to 40% of the total voltage and the DC quiescent voltage across the second transistor to be 70% - 60% of the total voltage; the unequal DC quiescent voltages across the first and second transistors causing a reduction of a second intermodulation product produced by the first and second transistors as compared with a second intermodulation product that would be produced by the first and second transistors operating with equal DC quiescent voltages across the first and second transistors.
10. 10. An improvement for an RF amplifier circuit operating within a range of frequencies having a low noise amplifier producing RF signals on an output and a load coupled to the output to receive the RF signals, the improvement comprising: a post distortion (PD) circuit having a semiconductor device with a control gate biased to cause the semiconductor device to operate in a nonlinear region at or near pinch-off; the PD circuit having a PD port that is coupled to the output of the low noise amplifier; the PD circuit generating at least one PD intermodulation product at the PD port in response to the RF signals being received from the low noise amplifier through the coupling by the PD circuit, the at least one PD intermodulation product being out of phase to an intermodulation product produced by the low noise amplifier that is present at the output; the at least one PD intermodulation product combining with the intermodulation product produced by the low noise amplifier to cause a reduction of the intermodulation product at the load by at least 10 dB for at least one frequency in the range of frequencies.
11. 11. The improvement of claim 10 further comprising the PD circuit being coupled to the low noise amplifier only by an AC coupling so that no DC power used by the low noise circuit is utilized by the PD circuit.
12. 12. The improvement of claim 10 wherein the at least one PD intermodulation product and the intermodulation product produced by the low noise amplifier are each second order intermodulation products.
13. 13. The improvement of claim 10 further comprising a DC bias circuit, coupled to the control gate of the active semiconductor device of the PD circuit, provides a biasing voltage that establishes a DC quiescent point substantially at or near pinch-off of the active semiconductor device.
14. 14. The improvement of claim 10 wherein the semiconductor device is a high electron mobility transistor (HEMT) having indium arsenide composite channel (IACC) technology.
15. 15. The improvement of claim 10 further comprising a resistor in series between the PD port and the output of the low noise amplifier, where a value of the resistor determines an amount of coupling between the PD circuit and the output of the low noise amplifier.
16. 16. The improvement of claim 10 further comprising at least one of an inductor and a capacitor connected between the PD port and the output of the low noise amplifier, where a value of the at least one inductor and capacitor contributes to determining a frequency with the range of frequencies where a maximum reduction of the intermodulation product at the load occurs.
17. 17. The improvement of claim 10 further comprising an inductor and a capacitor connected between the PD port and the output of the low noise amplifier, where values of the inductor and capacitor contributes to determining a frequency with the range of frequencies where a maximum reduction of the intermodulation product at the load occurs.
18. 18. An RF amplifier circuit operating within a range of frequencies comprising: a low noise amplifier producing RF signals including a second order intermodulation product on an output; a load coupled to the output to receive the RF signals and second order intermodulation product; the low noise amplifier having first and second transistors operating as a dual gate device; a bias circuit coupled to the first and second transistors establishes a DC quiescent voltage across each of the first and second transistors with the sum of the DC quiescent voltages across the first and second transistors being a total voltage; the bias circuit causing the DC quiescent voltage across the first transistor to be 30% to 40% of the total voltage and the DC quiescent voltage across the second transistor to be 70% - 60%, respectively, of the total voltage; the unequal DC quiescent voltages across the first and second transistors causing a reduction of the second intermodulation product produced by the first and second transistors as compared with a second intermodulation product produced by the first and second transistors operating with equal DC quiescent voltages across the first and second transistors.
19. 19. The RF amplifier circuit of claim 18 further comprising: a post distortion (PD) circuit having a semiconductor device with a control gate biased to cause the semiconductor device to operate in a nonlinear region at or near pinch-off; the PD circuit having a PD port that is AC coupled to the output of the low noise amplifier; the PD circuit generating a second order PD intermodulation product at the PD port in response to the RF signals being received from the low noise amplifier through the AC coupling by the PD circuit, the second order PD intermodulation product being out of phase to a second order intermodulation product produced by the low noise amplifier that is present at the output; the second order PD intermodulation product combining with the second order intermodulation product produced by the low noise amplifier to cause a reduction of the second order intermodulation product at the load by at least 10 dB for at least one frequency in the range of frequencies.
20. 20. The RF amplifier circuit of claim 19 further comprising a DC bias circuit, coupled to the control gate of the active semiconductor device of the PD circuit, provides a biasing voltage that establishes a DC quiescent point substantially at or near pinch-off of the active semiconductor device.

Description

LOW NOISE AMPLIFIER WITH POST DISTORTION CIRCUIT Background [01] Embodiments of the invention relate to low noise amplifiers (LNA) and in particular to LNAs where low second-order intermodulation products (IM2) are desired in order to meet stringent linearity requirements. [02] LNAs which operate in the gigahertz region and have high linearity requirements present significant challenges. These challenges can be exacerbated where the LNA is required to operate with low DC power consumption. Some technologies, e.g., Indium Phosphide (InP) and Indium Arsenide Composite Channel (IACC), are especially challenging when operated at low DC power. LNAs are often required to meet high standards for minimized second order intermodulation products (IM2) over a desired band of operation in order to achieve a desired level of linearity. [03] There exists a need for an LNA with minimized IM2 products in order to provide an improved second order intercept point (IP2) and enhanced linearity. Summary [04] It is an object of embodiments of the present invention to provide an improved LNA with minimized IM2 products in order to provide high linearity, with emphasis on improving second-order intercept point (e.g., IP2). [05] It is a further object of embodiments of the present invention to provide a post distortion circuit that operates in conjunction with an LNA to minimize IM2 products at the output of the LNA. [06] An exemplary RF amplifier circuit has a LNA with its output coupling RF signals to a load. A post distortion (PD) circuit having a semiconductor device with a control gate biased to cause the semiconductor device to operate in a nonlinear region at or near pinch-off that is coupled to the output of the LNA. The PD circuit generates at least one PD intermodulation product at the PD port in response to the RF signals being received from the LNA through the coupling. The at least one PD intermodulation product being out of phase to an intermodulation product produced by the LNA that is present at the output. The at least one PD intermodulation product combining with the intermodulation product produced by the LNA to cause a reduction of the intermodulation product at the load by at least by several dB for at least one frequency in the range of frequencies. In another embodiment, a PD circuit is coupled to the output of an LNA to cause a reduction of at least one intermodulation product of the LNA at the load. [07] In a further embodiment, an LNA utilizes a complementary pair of semiconductor devices QI and Q2 for amplification. QI and Q2 are biased so that the DC quiescent voltages across each are not equal causing a reduction of the second intermodulation product produced by QI and Q2 as compared with a second intermodulation product produced by QI and Q2 operating with equal DC quiescent voltages. Description of the Drawings [08] Features of exemplary embodiments of the invention will become apparent from the description, the claims, and the accompanying drawings in which: [09] FIG. 1 shows an embodiment of the present invention with a post distortion circuit connected to the output of an LNA; [10] FIG. 2 shows an exemplary embodiment of a post distortion circuit in accordance with the present invention; [11] FIG. 3 shows the post distortion circuit of FIG. 2 as an equivalent circuit; [12] FIGs. 4A - 4C are graphs showing exemplary gains associated with intermodulation products produced by the post distortion circuit; [13] FIG. 5 shows a schematic diagram of an embodiment of the present invention in accordance with FIG. 1 ; [14] FIGs. 6, 7 and 8 are graphs representing a two-tone test spectrum of the post distortion circuit operated with different Vgs of the active device of the post distortion circuit; [15] Fig. 9A is a graph of gain versus frequency for an LNA with post distortion circuit as shown in FIG. 4 with 3 curves corresponding with 3 different values of a characteristic; [16] Fig. 9B is a graph of OIP2 versus frequency for an LNA with post distortion circuit as shown in FIG. 4 where the 3 curves correspond respectively with the 3 different values associated with FIG. 9A; [17] Fig. 9C is a graph of OIP3 versus frequency for an LNA with post distortion circuit as shown in FIG. 4 where the 3 curves correspond respectively with the 3 different values associated with FIG. 9A; [18] Figs. 10A - IOC, 11A - 11C, 12A - 12C, 13A - 13C, and 14A - 14C correspond respectively to Figures 9A - 9C where the 3 curves in each graph correspond respectively with 3 different values as specified; [19] FIG. 15 is a graph of OIP 3 versus frequency for an LNA with post distortion circuit as shown in FIG. 4 where the 2 curves correspond respectively with the 2 different values associated with each; [20] FIG. 16 is a graph of OIP2 versus frequency for an LNA with post distortion circuit as shown in FIG. 4 where the 2 curves correspond respectively with the same 2 different values associated with respective curves in FIG. 15; [21