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EP-4736325-A1 - A CAPACITIVE DIGITAL-TO-ANALOG CONVERTER FOR MULTI-BAND RADIO FREQUENCY COMMUNICATION

EP4736325A1EP 4736325 A1EP4736325 A1EP 4736325A1EP-4736325-A1

Abstract

Disclosed herein are devices, methods, and systems that relate to wireless communications architectures and, in particular, multi-band radio-frequency circuitry. Disclosed herein is a capacitive digital-to-analog converter (CDAC). The CDAC may include a plurality of circuits configured to receive a digital signal to be converted into an analog signal, wherein each circuit of the plurality of circuits may include: a variable capacitive element; and a driver configured to cause the variable capacitive element to be charged or discharged to convert the received digital signal into the analog signal.

Inventors

  • DEGANI, OFIR
  • BEN-BASSAT, ASSAF

Assignees

  • INTEL Corporation

Dates

Publication Date
20260506
Application Date
20231227

Claims (20)

  1. 1. A capacitive digital-to-analog converter (CD AC) comprising: a plurality of circuits configured to receive a digital signal to be converted into an analog signal, wherein each circuit of the plurality of circuits comprises: a variable capacitive element; and a driver configured to cause the variable capacitive element to be charged or discharged to convert the digital signal into the analog signal.
  2. 2. The CD AC of claim 1, wherein each circuit further comprises a logic component configured to provide received digital signal to a signal path coupled to the driver based on a received control signal.
  3. 3. The CD AC of claim 1 or 2, wherein the CD AC comprises an output terminal coupled to the variable capacitive element of each circuit, wherein the variable capacitive element is a voltage-variable capacitive element.
  4. 4. The CDAC of claim 3, wherein a capacitance of the voltage-variable capacitive elements is controlled by a voltage applied to the output terminal.
  5. 5. The CD AC of claim 4, wherein the driver comprises an inverter, wherein the inverter is configured to provide an inverted digital signal varying between an upper voltage level and a lower voltage level, wherein the voltage applied to the output terminal is at the upper voltage level.
  6. 6. The CDAC of claim 4, wherein the driver comprises an inverter, wherein the inverter is configured to provide an inverted digital signal varying between an upper voltage level and a lower voltage level, wherein the voltage applied to the output terminal is at the lower voltage level.
  7. 7. The CDAC of any one of claims 3 to 6, wherein the voltage-variable capacitive element comprises a metal oxide semiconductor (MOS) varactor.
  8. 8. An apparatus of a digital communication circuit, the apparatus comprising: a controller; and a capacitive digital-to-analog converter (CDAC) comprising a plurality of circuits configured to receive a digital signal to be converted into an analog signal, wherein each circuit of the plurality of circuits comprises: a variable capacitive element; a driver configured to cause the variable capacitive element to be charged or discharged to convert the digital signal into the analog signal, wherein the controller is configured activate or deactivate each circuit of the plurality of circuits.
  9. 9. The apparatus of claim 8, wherein the controller is configured to activate or deactivate each circuit of the plurality of circuits based on amplitude control information.
  10. 10. The apparatus of claim 8 or 9, further comprising: a digital front end configured to provide the amplitude control information based on baseband signals.
  11. 11. The apparatus of any one of claims 8 to 10, wherein each circuit further comprises a further voltage-variable capacitive element configured to discharge to a further output terminal, and a further driver configured to drive the further voltage-variable capacitive element, wherein the further voltage-variable capacitive element and the further driver are provided in a differential signal path that is different from a signal path in which the voltagevariable capacitive element and the driver are provided.
  12. 12. The apparatus of any one of claims 8 to 11, wherein the variable capacitive element is a voltage-variable capacitive element, wherein the voltage-variable capacitive elements of the plurality of circuits are coupled to an output terminal, wherein the apparatus further comprises a transformer-based matching network comprising a transformer with a primary winding coupled to the output terminal.
  13. 13. The apparatus of claim 12, further comprising: a voltage supply circuit configured to supply a voltage to the output terminal.
  14. 14. The apparatus of claim 13, further comprising: a transformer coupled to the output terminal, wherein a primary winding of the transformer comprises a center tap, and wherein the voltage supply circuit is configured to supply the voltage to the center tap.
  15. 15. The apparatus of claim 13, wherein the voltage causes to control capacitance of at least one circuit of the plurality of circuits.
  16. 16. The apparatus of claim 13, wherein the controller is further configured to control the voltage supply circuit.
  17. 17. The apparatus of claim 16, wherein the controller is configured to control the supply voltage based on a frequency band of radio frequency (RF) signals, wherein the frequency band of RF signals comprises at least one of 2.4 GHz, 5 GHz, or 6 GHz.
  18. 18. The apparatus of claim 17, wherein the controller is configured to cause the voltage supply circuit to supply a first voltage for one of the frequency bands of RF signals and to cause the voltage supply circuit to supply a second voltage for another one of the frequency bands of RF signals.
  19. 19. The apparatus of any one of claims 8 to 18, further comprising an antenna port configured to receive output signals of the CD AC.
  20. 20. The apparatus of any one of claims 8 to 19, wherein the apparatus is a digital polar transmitter.

Description

A CAPACITIVE DIGITAL-TO-ANALOG CONVERTER FOR MULTI-BAND RADIO FREQUENCY COMMUNICATION Cross-reference to Related Applications This PCT Application claims priority to US non-provisional application 18/343,822, filed on June 29, 2023, the entire contents of which are incorporated herein by reference. Technical Field [0001] Various aspects of this disclosure relate to capacitive digital-to-analog converters, digital transmission circuits, and radio communication devices. Background [0002] Digital transmission (TX) architectures may be preferable for radio telecommunication due to their compactness, especially in terms of the die area, their scalability in advance complementary metal-oxide-semiconductors (CMOS), and improved power efficiency, in particular, due to the use of digital power amplifiers (DP As). One type of DP As used in such digital TX architectures is a switched capacitor DPA (SCDPA). SCPDAs may be preferable in various operations due to their high efficiency, low distortion, and reduced size and costs compared to traditional PAs. [0003] An SCDPA may include a switched capacitor network that may be used to convert an input signal to a high-voltage signal, which may be then amplified by a PA stage. The switched capacitor network may include any type of capacitive units as capacitors. In a radio communication circuit architecture configured for multi-band radio frequency (RF) operation, separate DP As (e.g. SCDPAs) may be employed for different bands of frequencies, since it may be challenging to support multi-band RF operation in an effective manner with desired characteristics. Brief Description of Figures [0004] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the disclosure. In the following description, various aspects of the disclosure are described with reference to the following drawings, in which: FIGs. 1 and 2 depict a general network and device architecture for wireless communications; FIG. 3 shows an exemplary illustration of various communication elements of an apparatus for a wireless communication device; FIG. 4 shows an exemplary illustration of a transmit path of an RF transceiver; FIG. 5 schematically shows an example of an SCDPA; FIG. 6 illustrates an example of a driver of an SCDPA with 2-level transistor stacking to drive capacitors of an SCDPA cell; FIG. 7 shows schematically an example of a capacitive RF digital to power converter circuit; FIG. 8 shows an exemplary graph representative of an approximate relationship between the capacitance of a voltage-controlled capacitive element and Vtune voltage of a voltage-controlled capacitive element; FIG. 9 shows schematically an example of an apparatus of a digital communication circuit; FIG. 10 is a network diagram illustrating an example network environment including communication devices; FIG. 11 shows schematically load-pull simulation results obtained with a DPA in accordance with aspects provided herein; FIG. 12 shows schematically load-pull simulation results obtained with a DPA in accordance with aspects provided herein; FIG. 13 shows schematically load-pull simulation results obtained with a DPA in accordance with aspects provided herein; and FIG 14 shows schematically frequency response graphs of a DPA in accordance with aspects provided herein. Description [0005] PAs may be used in RF circuits to provide amplification to communication signals. In DTX architectures, PAs may be employed by DP As such as SCDPAs. An SCDPA may include a switched capacitor network that is configured to convert an input signal to a high-voltage, low- current signal. The switched capacitor network may include multiple capacitors and switches that may be selectively controlled to charge and discharge the capacitors. Through control of charging and discharging the capacitors, the output signal may be provided at a desired amplitude or power. A control circuit (e.g. a digital signal processor (DSP)) may be employed for controlling the timing and sequencing of switches. The output of the SCDPA may be provided to the next component/circuit (e.g. a matching network, an antenna interface, an antenna structure). [0006] Conventionally, an SCDPA may be implemented by a segmentation of an array including multiple cells. Each cell may include a capacitor, one or more logic for activating/deactivating the cell, and an inverter to provide inverted signal to the capacitor. The inverter may be to drive the capacitor. The inverter may include transistors (e.g. field effect transistors (FETs)) configured to drive the capacitor. A controller may control operation of the SCDPA. In particular, the controller may control output signal power of the SCDPA by selectively and/or adaptively activating (or selectively and/or adaptively deactivating) the cells. Activated cells may contribute to