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EP-4736326-A1 - MULTI-POINT REFERENCE DISTRIBUTION CIRCUIT

EP4736326A1EP 4736326 A1EP4736326 A1EP 4736326A1EP-4736326-A1

Abstract

A circuit includes an amplifier, a pre-driver circuit, and an output circuit (206). The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit (206) includes a first transistor (228) and a second transistor (230). The first transistor (228) has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor (230) has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor (228), and a second terminal coupled to a reference terminal.

Inventors

  • GHOSH, SOVAN
  • PENTAKOTA, Visvesvaraya, Appala

Assignees

  • Texas Instruments Incorporated

Dates

Publication Date
20260506
Application Date
20240626

Claims (20)

  1. CLAIMS What is claimed is: 1. A circuit comprising: an amplifier having first and second inputs and an output; a first transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal; a second transistor having a first terminal, a second terminal coupled to the first terminal of the first transistor, and a control terminal; a third transistor having a first terminal, a second terminal coupled to the second input of the amplifier, and a control terminal coupled to the second terminal of the second transistor; a fourth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal; a fifth transistor having a control terminal, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal coupled to a reference terminal; and a sixth transistor having a control terminal coupled to the first terminal of the fifth transistor, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the reference terminal.
  2. 2. The circuit of claim 1, further comprising: a seventh transistor having a control terminal coupled to the first terminal of the first transistor, a first terminal, and a second terminal coupled to the second terminal of the third transistor.
  3. 3. The circuit of claim 2, further comprising: an eighth transistor having a first terminal coupled to the first terminal of the third transistor, a second terminal coupled to the control terminal of the seventh transistor, and a control terminal coupled to the control terminal of the second transistor; and a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output of the amplifier.
  4. 4. The circuit of claim 2, further comprising: an eighth transistor having a control terminal coupled to the first terminal of the sixth transistor, a first terminal coupled to the second terminal of the seventh transistor, and a second terminal coupled to the reference terminal.
  5. 5. The circuit of claim 4, further comprising: a ninth transistor having a first terminal coupled to the first terminal of the third transistor, a second terminal coupled to the control terminal of the eighth transistor, and a control terminal coupled to the output of the amplifier; and a tenth transistor having a first terminal coupled to the second terminal of the ninth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the control terminal of the fifth transistor.
  6. 6. The circuit of claim 4, further comprising: a first resistor and a first capacitor coupled in series between the control terminal of the seventh transistor and a reference terminal; and a second resistor and a second capacitor coupled in series between the control terminal of the eighth transistor and the reference terminal.
  7. 7. The circuit of claim 1, further comprising: a first resistor and a first capacitor coupled in series between the control terminal of the third transistor and a reference terminal; and a second resistor and a second capacitor coupled in series between the control terminal of the sixth transistor and the reference terminal.
  8. 8. A circuit comprising: an amplifier having a first input, a second input, and an output; a pre-driver circuit having an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier; and an output circuit including: a first transistor having a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit; and a second transistor having a control terminal coupled to the second output of the pre- driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.
  9. 9. The circuit of claim 8, wherein the pre-driver circuit includes: a third transistor having a control terminal coupled to the output of the amplifier, a first terminal configured as the first output of the pre-driver circuit, and a second terminal coupled to a reference terminal; a fourth transistor having a first terminal, and a second terminal coupled to the first terminal of the third transistor, and a control terminal; and a fifth transistor having a first terminal, a second terminal coupled to the second input of the amplifier, and configured as the third output of the pre-driver circuit, and a control terminal coupled to the second terminal of the fourth transistor; a sixth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal configured as the second output of the pre-driver circuit; a seventh transistor having a control terminal, a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the reference terminal; and an eighth transistor having a control terminal coupled to the first terminal of the seventh transistor, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the reference terminal.
  10. 10. The circuit of claim 9, wherein the pre-driver circuit includes: a first snubber circuit coupled to the control terminal of the fifth transistor; and a second snubber circuit coupled to the control terminal of the eighth transistor.
  11. 11. The circuit of claim 8, wherein the output circuit includes: a third transistor having a first terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal coupled to a first bias voltage circuit; and a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output of the amplifier.
  12. 12. The circuit of claim 8, wherein the output circuit includes: a third transistor having a first terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the output of the amplifier; and a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to a second bias voltage circuit.
  13. 13. The circuit of claim 8, further comprising: a first snubber circuit coupled to the control terminal of the first transistor; and a second snubber circuit coupled to the control terminal of the second transistor.
  14. 14. An analog-to-digital converter (ADC) comprising: a first capacitive digital-to-analog converter (CDAC) having an input; a second CDAC having an input; a reference buffer coupled to the first CDAC and the second CDAC, the reference buffer including: an amplifier having a first input, a second input, and an output; a pre-driver circuit having an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier; and an output circuit including: a first transistor having a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the first CDAC; a second transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal; a third transistor having a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the second CDAC; and a fourth transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a reference terminal.
  15. 15. The ADC of claim 14, wherein the pre-driver circuit includes: a fifth transistor having a control terminal coupled to the output of the amplifier, a first terminal configured as the first output of the pre-driver circuit, and a second terminal coupled to a reference terminal; a sixth transistor having a first terminal, and a second terminal coupled to the first terminal of the fifth transistor, and a control terminal; and a seventh transistor having a first terminal, a second terminal coupled to the second input of the amplifier, and configured as the third output of the pre-driver circuit, and a control terminal coupled to the second terminal of the sixth transistor; an eighth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal configured as the second output of the pre-driver circuit; a ninth transistor having a control terminal, a first terminal coupled to the second terminal of the eighth transistor, a second terminal coupled to the reference terminal; a tenth transistor having a control terminal coupled to the first terminal of the ninth transistor, a first terminal coupled to the second terminal of the seventh transistor, and a second terminal coupled to the reference terminal; a first snubber circuit coupled to the control terminal of the seventh transistor; and a second snubber circuit coupled to the control terminal of the tenth transistor.
  16. 16. The ADC of claim 14, wherein the output circuit includes: a fifth transistor having a first terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal coupled to a first bias voltage circuit; and a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the third output of the pre-driver circuit.
  17. 17. The ADC of claim 14, wherein the output circuit includes: a fifth transistor having a first terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the third output of the pre-driver circuit; and a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to a second bias voltage circuit.
  18. 18. The ADC of claim 14, wherein the output circuit includes: a fifth transistor having a first terminal, a second terminal coupled to the control terminal of the third transistor, and a control terminal coupled to a first bias voltage circuit; and a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the third output of the pre-driver circuit.
  19. 19. The ADC of claim 14, wherein the output circuit includes: a fifth transistor having a first terminal, a second terminal coupled to the control terminal of the fourth transistor, and a control terminal coupled to the third output of the pre-driver circuit; and a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to a second bias voltage circuit.
  20. 20. The ADC of claim 14, further comprising: a first snubber circuit coupled to the control terminal of the first transistor; a second snubber circuit coupled to the control terminal of the second transistor; a third snubber circuit coupled to the control terminal of the third transistor; and a fourth snubber circuit coupled to the control terminal of the fourth transistor.

Description

MULTI-POINT REFERENCE DISTRIBUTION CIRCUIT BACKGROUND [0001] Various types of analog-to-digital converters (ADCs) such as successive-approximation- register (SAR) ADCs, Sigma-Delta ADCs, and pipelined ADCs include a capacitive digital-to- analog converter (DAC) as a circuit element. For example, in a SAR ADC, during a conversion process, a capacitive DAC is periodically switched during the conversion process to generate analog voltage levels for comparison with a sampled input signal. Inputs of the capacitive DAC are successively switched to either a reference voltage or ground, thereby drawing current from the reference voltage source. The current drawn by the capacitive DAC can vary with the input signal. The variation in current drawn by capacitive DAC may induce nonlinearity in the reference voltage. SUMMARY [0002] In one example, a circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The amplifier has first and second inputs and an output. The first transistor has a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal. The second transistor has a first terminal, a second terminal coupled to the first terminal of the first transistor, and a control terminal. The third transistor has a first terminal, a second terminal coupled to the second input of the amplifier, and a control terminal coupled to the second terminal of the second transistor. The fourth transistor has a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal. The fifth transistor has a control terminal, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal coupled to a reference terminal. The sixth transistor has a control terminal coupled to the first terminal of the fifth transistor, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the reference terminal. [0003] In another example, a circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal. [0004] In a further example, an analog-to-digital converter (ADC) includes a first capacitive digital-to-analog converter (CDAC), a second CDAC, and a reference buffer. The first CDAC has an input. The second CDAC has an input. The reference buffer is coupled to the first CDAC and the second CDAC. The reference buffer includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the first CDAC. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal. The third transistor has a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the second CDAC. The fourth transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to a reference terminal. BRIEF DESCRIPTION OF THE DRAWINGS [0005] FIG. 1 is a block diagram of an analog-to-digital converter that includes a multi-point reference distribution circuit. [0006] FIGS. 2A and 2B are a schematic diagram of a first multi-point reference distribution circuit suitable for use in the analog-to-digital converter of FIG.1. [0007] FIGS.3A and 3B are a schematic diagram of a second multi-point reference distribution circuit suitable for use in the analog-to-digit