EP-4736327-A2 - PROCESSING NODES FOR SIGNAL PROCESSING IN RADIO TRANSCEIVERS

Abstract

Radio systems and transceivers are described with a software defined physical layer (SDP) architecture that incorporate processing nodes with existing hardware blocks. The processing nodes provide a soft-processing design that supports existing functionality and also enables future updates to provide additional and/or improved flexibility. The processing nodes can be added to existing hardware designs to support existing functionality, providing additional processing power to existing hardware blocks when requested or needed, and to provide expanded capabilities by taking over certain functions performed by existing hardware blocks or by replacing the existing hardware blocks in the processing chain. The processing nodes allow radio systems to maintain their core design while adding a soft-processing design that can assist in performing the core tasks of the hardware blocks and that can eventually take over and replace the functionality of the hardware blocks.

Inventors

• SISODIA, Vrishbhan Singh
• DAVE, SAMEEP

Assignees

• Viasat, Inc.

Dates

Publication Date

20260506

Application Date

20240726

Claims (20)

1. 1 . A processing node (PN) comprising: a first digital signal processor (DSP) core; a second DSP core; a plurality of extended direct memory access controllers (DCX), each DOX having shared memory space, an input packet interface, and an output packet interface, the input packet interface configured to receive samples from a hardware block separate from the processing node, the shared memory space configured to store the received samples, and the output packet interface configured to transmit samples processed by the first DSP core or the second DSP core to the hardware block; and a PN network interconnect configured to communicably couple the first DSP core, the second DSP core, and the plurality of DCX, each DSP core and DCX coupled to the PN network interconnect through a respective master interface and a respective slave interface, the PN network interconnect further including an SDP master interface and an SDP slave interface each configured to communicate with an SDP network interconnect, wherein the processing node is configured to be integrated into a radio transceiver comprising the hardware block and to interface with the hardware block to provide configurable processing functionality to the radio transceiver.
2. 2. The processing node of claim 1 , wherein the PN network interconnect further includes a configuration interface configured to enable the processing node to configure the hardware block.
3. 3. The processing node of claim 1 further comprising a queue interface configured to transfer commands or data from the first DSP core to the second DSP core and to transfer commands or data from the second DSP core to the first DSP core.
4. 4. The processing node of claim 1 further comprising a first queue interface and a second queue interface, the first queue interface configured to transfer commands or data from the first DSP core to the second DSP core, the second queue interface configured to transfer commands or data from the second DSP core to the first DSP core.
5. 5. The processing node of claim 1 , wherein each DSP core includes a general-purpose input-output (GPIO) port connected to a configuration register and configured to receive input for placement in the configuration register and to transmit data stored in the configuration register.
6. 6. The processing node of claim 1 , wherein each DSP core is configured to receive interrupt requests through the PN network interface from the hardware block that is separate from the processing node.
7. 7. The processing node of claim 1 , wherein a first DCX of the plurality of DCX is configured to: receive a plurality of samples, from a first hardware block, to be processed through the input packet interface; temporarily store the plurality of samples in the shared memory space; and transmit the plurality of samples to the first DSP core through the PN network interconnect.
8. 8. The processing node of claim 7, wherein the first DSP core or the second DSP core is configured to: program the first DCX to convey the plurality of samples to the first DSP core; place the plurality of samples into an internal memory space of the first DSP core; process the plurality of samples; and place the processed samples into the internal memory space of the first DSP core.
9. 9. The processing node of claim 7, wherein the first DCX is further configured to reformat the received plurality of samples.
10. 10. The processing node of claim 9, wherein the first DCX is configured to reformat the received plurality of samples by sign extending samples of the received plurality of samples to increase the number of bits for each sample.
11. 1 1 . The processing node of claim 9, wherein the first DCX is configured to reformat the received plurality of samples by bit clipping samples of the received plurality of samples to reduce a resolution of each sample.
12. 12. The processing node of claim 1 , wherein a first DCX of the plurality of DCX is configured to: receive a plurality of samples to be processed through the input packet interface; temporarily store the plurality of samples in the shared memory space; and transmit the plurality of samples to the hardware block separate from the processing node for processing using the output packet interface.
13. 13. The processing node of claim 12, wherein the first DCX is configured to: receive the processed plurality of samples from the hardware block; and temporarily store the processed plurality of samples in the shared memory space.
14. 14. The processing node of claim 1 , wherein the first DSP core and the second DSP core are configured to be used both as separate entities and as a shared dual-core configuration.
15. 15. The processing node of claim 1 , wherein the first DSP core and the second DSP core each include two processors and the plurality of DCX includes a DCX for each processor of the first DSP core and the second DSP core.
16. 16. The processing node of claim 1 , wherein the SDP master interface and the SDP slave interface of the PN network interconnect are configured to communicate with a PN network interconnect of a different processing node in the radio transceiver via the SDP network interconnect.
17. 17. The processing node of claim 1 , wherein the first DSP core, the second DSP core, and each of the plurality of DCX includes a configuration register configured to store data to configure the associated DSP core or DCX.
18. 18. The processing node of claim 1 , wherein the processing node is configured to be implemented within a demodulator of the radio transceiver.
19. 19. The processing node of claim 1 , wherein the processing node is configured to be implemented within a decoder of the radio transceiver.
20. 20. The processing node of claim 1 , wherein the processing node is configured to be implemented within a modulator or encoder of a transmitter of the radio transceiver.

Description

PROCESSING NODES FOR SIGNAL PROCESSING IN RADIO TRANSCEIVERS CROSS-REFERENCE TO RELATED APPLICATION(S) [0001] This application claims the benefit of priority to U.S. Prov. App. No. 63/516,434 filed July 28, 2023 and entitled PROCESSING NODES FOR SIGNAL PROCESSING IN RADIO TRANSCEIVERS, the entire contents of which is incorporated by reference in its entirety for all purposes. BACKGROUND Field [0002] The present disclosure generally relates to processing nodes for signal processing in radio transceivers. Description of Related Art [0003] Signal processing in a radio transceiver involves various operations to manipulate and enhance received and transmitted signals. A radio transceiver can receive an analog radio-frequency (RF) signal and convert it into a digital signal via analog to digital conversion (ADC) and relatedly, the radio transceiver can convert a digital signal ready for transmission via digital to analog conversion (DAC). Digital signal processing includes the processing steps performed on the digital signal (e.g., after processing by the ADC and/or before processing by the DAC). Digital signal processing can be applied to extract, filter, and enhance useful information in the signal. This processing may include processes or operations such as filtering, equalization, modulation, demodulation, channel coding or decoding, error correction, and noise reduction. Other processes that can be performed include frequency conversion (e.g., converting to a baseband frequency or to a carrier frequency), gain control, amplification, and the like. SUMMARY [0004] According to a number of implementations, the present disclosure relates to a processing node (PN) that includes a first digital signal processor (DSP) core; a second DSP core; a plurality of extended direct memory access controllers (DCX), each DCX having shared memory space, an input packet interface, and an output packet interface, the input packet interface configured to receive samples from a hardware block separate from the processing node, the shared memory space configured to store the received samples, and the output packet interface configured to transmit samples processed by the first DSP core or the second DSP core to the hardware block; and a PN network interconnect configured to communicably couple the first DSP core, the second DSP core, and the plurality of DCX, each DSP core and DCX coupled to the PN network interconnect through a respective master interface and a respective slave interface, the PN network interconnect further including an SDP master interface and an SDP slave interface each configured to communicate with an SDP network interconnect. The processing node is configured to be integrated into a radio transceiver comprising the hardware block and to interface with the hardware block to provide configurable processing functionality to the radio transceiver. [0005] In some embodiments, the PN network interconnect further includes a configuration interface configured to enable the processing node to configure the hardware block. In some embodiments, the processing node further includes a queue interface configured to transfer commands or data from the first DSP core to the second DSP core and to transfer commands or data from the second DSP core to the first DSP core. In some embodiments, the processing node further includes a first queue interface and a second queue interface, the first queue interface configured to transfer commands or data from the first DSP core to the second DSP core, the second queue interface configured to transfer commands or data from the second DSP core to the first DSP core. [0006] In some embodiments, each DSP core includes a general-purpose input-output (GPIO) port connected to a configuration register and configured to receive input for placement in the configuration register and to transmit data stored in the configuration register. In some embodiments, each DSP core is configured to receive interrupt requests through the PN network interface from the hardware block that is separate from the processing node. [0007] In some embodiments, a first DCX of the plurality of DCX is configured to: receive a plurality of samples, from a first hardware block, to be processed through the input packet interface; temporarily store the plurality of samples in the shared memory space; and transmit the plurality of samples to the first DSP core through the PN network interconnect. In some embodiments, the first DSP core or the second DSP core is configured to: program the first DCX to convey the plurality of samples to the first DSP core; place the plurality of samples into an internal memory space of the first DSP core; process the plurality of samples; and place the processed samples into the internal memory space of the first DSP core. In some embodiments, the first DCX is further configured to reformat the received plurality of samples. In some embodiments, the first DCX is configured to reformat the