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EP-4736594-A1 - SEMICONDUCTOR STRUCTURES

EP4736594A1EP 4736594 A1EP4736594 A1EP 4736594A1EP-4736594-A1

Abstract

A CAVET comprises: a drain terminal (110); a source terminal (170); and a current blocking layer (240), CBL, between the drain terminal and the source terminal, wherein the CBL comprises at least one porous region (244, 246) for blocking current between the source terminal and the drain terminal and a non-porous aperture region (242) for allowing current flow between the source terminal and the drain terminal.

Inventors

  • HAMMOND, RICHARD
  • GOKTEPELI, SINAN

Assignees

  • IQE plc

Dates

Publication Date
20260506
Application Date
20240530

Claims (20)

  1. 1. A CAVET comprising: a drain terminal; a source terminal; and a current blocking layer, CBL between the drain terminal and the source terminal, wherein the CBL comprises at least one porous region for blocking current between the source terminal and the drain terminal and a non-porous aperture region for allowing current flow between the source terminal and the drain terminal.
  2. 2. The CAVET according to claim 1 wherein the at least one porous region comprises a first porous region and a second porous region disposed either side of the aperture region.
  3. 3. The CAVET according to claim 2 comprising a first source terminal and a second source terminal; and wherein the first source terminal is over the first porous region and the second source terminal is over the second porous region.
  4. 4. The CAVET according to any preceding claim wherein the at least one porous region comprises a plurality of porous sub-regions separated from each other by a plurality of non-porous sub-regions.
  5. 5. The CAVET according to claim 4 wherein the aperture region comprises a plurality of second sub-regions separated by the plurality of non-porous subregions.
  6. 6. The CAVET according to any preceding claim further comprising a gate terminal over the CBL; and wherein edges of the gate terminal overlap with edges of the aperture region.
  7. 7. The CAVET according to any preceding claim wherein the at least one porous region comprises an oxidized porous region.
  8. 8. The CAVET according to any preceding claim further comprising a plurality of III- N semiconductor layers comprising the CBL.
  9. 9. The CAVET according to any preceding claim wherein the at least one porous region comprises a greater concentration of n-type dopants than the non-porous aperture region.
  10. 10. A semiconductor structure comprising: a substrate; and a plurality of semiconductor layers over the substrate comprising a first III- N semiconductor layer comprising a porous region and a non-porous region.
  11. 11. The semiconductor structure according to claim 10 wherein the porous region comprises a plurality of porous sub-regions separated from each other by a plurality of non-porous sub-regions.
  12. 12. The semiconductor structure according to claim 10 or 11 wherein the non-porous region comprises a plurality of second sub-regions separated by the plurality of non-porous sub-regions.
  13. 13. The semiconductor structure according to any of claims 10-12 wherein the at least one porous region comprises a greater concentration of n-type dopants than the non-porous region.
  14. 14. The semiconductor structure according to any of claims 10-13 wherein the porous region comprises an oxidized porous region.
  15. 15. The semiconductor structure according to any of claims 10-14 wherein the first semiconductor layer comprises a current blocking layer, CBL, and wherein the plurality of semiconductor layers comprise: a drain semiconductor layer; a drift layer over the drain semiconductor layer; the CBL over the drain semiconductor layer, a channel layer over the CBL; and a barrier layer over the channel layer.
  16. 16. The semiconductor structure according to claim 15 wherein the plurality of semiconductor layers comprise lll-N semiconductor material.
  17. 17. A semiconductor device comprising the semiconductor structure according to any of claims 10-16.
  18. 18. A power management device comprising the semiconductor device according to claim 17 or the CAVET according to any of claims 1-9.
  19. 19. An electronic device comprising the power management device according to claim 18.
  20. 20. A vehicle comprising the power management device according to claim 18.

Description

SEMICONDUCTOR STRUCTURES Technical field The present application relates to a current aperture vertical electron transistor (CAVET). The present application also relates to a semiconductor structure and method for forming a semiconductor structure. Background There is increasing interest in forming semiconductor devices such as transistors from Ill-N semiconductor materials. Ill-N semiconductor materials, such as GaN, possess desirable electronic properties, such as a high breakdown voltage and high critical electric field. A popular semiconductor device formed from Ill-N semiconductor materials, such as GaN, is the high electron mobility transistor (HEMT). A HEMT comprises a two- dimensional electron gas (2DEG) for carrier flow between the source and the drain, which is attractive due to the high electron mobility of the 2DEG. A HEMT commonly has a lateral semiconductor device architecture where the source terminal and drain terminal are formed on the same side of a semiconductor wafer, either side of the gate terminal. Current flow thus occurs in a lateral direction from the source to the drain and is regulated by the gate terminal. In some applications, a lateral HEMT architecture can suffer from drawbacks. For example, in high power applications, the gate-to-drain terminal spacing is relatively large, thus increasing the footprint of the device. It can therefore be desirable to form semiconductor devices with a vertical architecture with the source and drain terminal disposed on opposite sides of a semiconductor wafer. One Ill-N based semiconductor device with a vertical architecture is the current aperture vertical electron transistor (CAVET). In a CAVET, a source terminal and a drain terminal are formed on opposite sides of a semiconductor wafer. Current flow thus takes place in a vertical direction through the CAVET from the source terminal to the drain terminal. Figure 1 illustrates one example of a CAVET 100. CAVET 100 includes a drain terminal 110 fabricated on a n-type semiconductor layer 120, which is some examples may be termed a drain semiconductor layer. CAVET 100 further comprises a drift layer 130 over the n-type semiconductor layer 120 and a current blocking layer (CBL) 140 over the drift layer 130. The CBL 140 comprises an aperture 142 for allowing a flow of current and a first current blocking portion 144 and a second current blocking portion 146 for blocking current flow. The CAVET 100 further comprises a channel layer 150 over the CBL 140 and a barrier layer 160 over the channel layer. A 2DEG 152 is formed within the channel layer 150. The CAVET 100 further comprises a first source terminal 170 and a second source terminal 180 fabricated on the channel layer 150. The CAVET 100 further comprises a gate terminal fabricated on the barrier layer 160. In operation, a bias voltage applied to the gate terminal 190 may be controlled to prevent or allow current flow between the source terminals 170, 180 and the drain terminal 110. For example, in a depletion mode operation, removal of a bias voltage from the gate terminal 190 may allow charge carriers to flow from the source terminals 170, 180 to the drain terminal 110. In such examples, charge carriers travel along the 2DEG 152 in the channel layer 150 in a lateral direction under the gate terminal 190. Carriers can then drift towards the drain terminal 110 through the aperture 142 to allow current flow through the CAVET 100 in a vertical direction. The CBL 140 and, in particular, the current blocking portions 144, 146, prevent carriers drifting from source terminals 170, 180 directly towards the drain terminal 110 through the drift layer 130. This effect by the current blocking portions 144, 146 maintains the formation of the 2DEG 152, enabling the high electron mobility of the CAVET 100. The first and second current blocking portions 144, 146 may thus comprise a material for blocking carrier flow. In some examples, the first and second current blocking portions 144, 146 may comprise epitaxially deposited SiN. The architecture of the CAVET leads to many advantages over a lateral semiconductor device architecture, such as a reduced footprint, low voltage gate control, high critical electric field and high mobility. Whilst the CAVET has many advantages, it has not found wide spread use in many applications due to the fabrication process used to for a CAVET. The fabrication of the CAVET 100 first involves epitaxially growing the drain semiconductor layer 120 and the drift layer 130 on a substrate. The semiconductor structure formed on the substrate may be termed a wafer from which many CAVETs may be fabricated. Material to form the CBL 140 is then epitaxially grown on the drift layer 130. In such examples, the material may comprise SiN. The SiN material may then be masked to provision the regions where aperture 142 is to be formed. The SiN is subsequently etched to form the aperture 142. The remaining SiN thus forms the current blocking port