EP-4736595-A1 - SEMICONDUCTOR DEVICE WITH NITROGEN DOPED FIELD RELIEF DIELECTRIC LAYER

Abstract

Semiconductor devices including a nitrogen doped field relief dielectric layer (130) are described. The microelectronic device (100) comprises a substrate (103) including a body region (108) having a first conductivity type and a drain drift region (138) having a second conductivity type opposite the first conductivity type; a gate dielectric layer (150) on the substrate (103), the gate dielectric layer (150) extending over the body region, (108) the drain drift region, (138) and a nitrogen doped field relief dielectric layer (130) on the drain drift region (138).

Inventors

• BAUER, JACKSON
• PAN, Yanbiao
• SRINIVASAN, BHASKAR
• MAHALINGAM, PUSHPA

Assignees

• Texas Instruments Incorporated

Dates

Publication Date

20260506

Application Date

20231229

Claims (20)

1. 1. A semiconductor device, comprising: a semiconductor material of a substrate, the semiconductor material including a body region having a first conductivity type and a drain drift region having a second conductivity type; a doped field relief dielectric layer over the drain drift region, the doped field relief dielectric layer including primarily silicon dioxide and includes at least 5 atomic percent nitrogen, the doped field relief dielectric layer extending from a gate dielectric layer toward a drain region and having a thickness greater than the gate dielectric layer; wherein the gate dielectric layer over the body region extends over an intersection between the body region and the drain drift region; a gate electrode over the gate dielectric layer; and a drain region having the second conductivity type contacting the drain drift region, the drain region having an average dopant density greater than an average dopant density of the drain drift region.
2. 2. The semiconductor device of claim 1, wherein the doped field relief dielectric layer includes a local oxidation of silicon (LOCOS) layer of silicon dioxide including at least 5 atomic percent nitrogen and including a tapered edge.
3. 3. The semiconductor device of claim 1, wherein the doped field relief dielectric layer includes a shallow trench isolation (STI) layer of silicon dioxide including at least 5 atomic percent nitrogen.
4. 4. The semiconductor device of claim 1 wherein a portion of an atomic percent nitrogen in the doped field relief dielectric layer is a constituent of silicon nitride.
5. 5. The semiconductor device of claim 1 wherein a portion of an atomic percent nitrogen in the doped field relief dielectric layer is a constituent of silicon oxynitride.
6. 6. The semiconductor device of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.
7. 7. The semiconductor device of claim 1, wherein an atomic percent nitrogen of the doped field relief dielectric layer is more concentrated at a top surface of the doped field relief dielectric layer than at an interface between the doped field relief dielectric layer and the substrate.
8. 8. The semiconductor device of claim 1, wherein an atomic percent nitrogen of the doped field relief dielectric layer has an approximately uniform concentrated of atomic percent nitrogen throughout doped field relief dielectric layer.
9. 9. The semiconductor device of claim 1, wherein the gate electrode has a closed-loop configuration.
10. 10. The semiconductor device of claim 1 wherein a doped field oxide includes at least 5 atomic percent nitrogen.
11. 11. A method of forming a microelectronic device, comprising: forming a body region and a drain drift region in a semiconductor material of a substrate, the body region having a first conductivity type and the drain drift region having a second conductivity type; forming a doped field relief dielectric layer over the drain drift region, the doped field relief dielectric layer having greater than 5 atomic percent nitrogen and a thickness greater than a gate dielectric layer; forming the gate dielectric layer over the body region, the gate dielectric layer extending over an intersection between the body region and the drain drift region; forming a gate electrode over the gate dielectric layer; forming a source region having the second conductivity type contacting the body region, the source region having an average dopant density greater than the average dopant density of the body region; and forming a drain region having the second conductivity type contacting the drain drift region, the drain region having an average dopant density greater than an average dopant density of the drain drift region.
12. 12. The method of claim 11, wherein a field relief dielectric layer is formed by local oxidation of silicon (LOCOS).
13. 13. The method of claim 11, wherein a field relief dielectric layer is formed by shallow trench isolation (STI).
14. 14. The method of claim 11, wherein a doped field relief dielectric layer is formed by a nitrogen containing plasma including dinitrogen (N2) which incorporates an atomic percent nitrogen into a field relief dielectric layer.
15. 15. The method of claim 11, wherein a dope field relief dielectric layer is formed by a nitrogen containing plasma including ammonia (NH3) which incorporates an atomic percent nitrogen into a field relief dielectric layer.
16. 16. The method of claim 11, wherein a doped field relief dielectric layer is formed by a dielectric deposition process including at least one nitrogen containing precursor.
17. 17. The method of claim 11, wherein the doped field relief dielectric layer and a doped field oxide layer are formed concurrently.
18. 18. The method of claim 11, wherein a portion of an atomic percent nitrogen in the doped field relief dielectric layer is formed by a nitrogen containing plasma as silicon nitride.
19. 19. The method of claim 11 wherein a portion of an atomic percent nitrogen in the doped field relief dielectric layer is formed by a nitrogen containing plasma as silicon oxynitride.
20. 20. The method of claim 11, wherein an atomic percent nitrogen of the doped field relief dielectric layer is formed with a higher concentration of nitrogen at a top surface of the doped field relief dielectric layer than at an interface between the doped field relief dielectric layer and the substrate.

Description

SEMICONDUCTOR DEVICE WITH NITROGEN DOPED FIELD RELIEF DIELECTRIC LAYER [0001] This disclosure relates to the field of microelectronic devices. More particularly, but not exclusively, this disclosure relates to microelectronic devices having a nitrogen doped field relief dielectric layer. BACKGROUND [0002] Semiconductor components are being continually improved to reliably operate with smaller feature sizes. Fabricating semiconductor devices that have increasingly higher performance while meeting reliability specifications is challenging. SUMMARY [0003] This summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the detailed description including the drawings provided. This summary is not intended to limit the claimed subject matter’s scope. [0004] Disclosed examples include a microelectronic device with a nitrogen doped field relief dielectric layer. The nitrogen doped field relief dielectric layer is a primarily silicon dioxide layer which has an atomic percent nitrogen content which may be in the form silicon oxynitride, silicon nitride, or interstitial nitrogen species or any combination thereof. The microelectronic device comprises a substrate including a body region having a first conductivity type and a drift region having a second conductivity type opposite the first conductivity type; a gate dielectric layer on the substrate, the gate dielectric layer extending over an intersection of the body region and the drift region; a field relief dielectric layer on the drift region, the field relief dielectric layer laterally abutting the gate dielectric layer at a location in the drift region, and a gate electrode on the gate dielectric layer and the field relief dielectric layer. [0005] The doping of the field relief dielectric layer with nitrogen raises the dielectric constant of the field relief dielectric above that of pure silicon dioxide. By increasing the dielectric constant of the field relief dielectric layer, channel hot carrier performance may be improved, breakdown resistance may be improved, and specific on resistance of the microelectronic device may be lowered compared to a microelectronic device of similar size with a field relief dielectric which is not doped with nitrogen. The microelectronic device also includes a source region disposed in the body region, the source region having the second conductivity type; and a drain region disposed in the drift region, the drain region having the second conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIG. 1A through FIG. IL are cross sections of an example microelectronic device including a transistor with a nitrogen doped field relief dielectric layer in various stages of formation. [0007] FIG. 2 is a top-down view of an example microelectronic device including a transistor with a nitrogen doped field relief dielectric layer. [0008] FIG. 3 is a cross section of an alternate example microelectronic device including a transistor with a nitrogen doped field relief dielectric layer including shallow trench isolation. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS [0009] The present disclosure is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure. [0010] In addition, although some of the embodiments illustrated herein are shown in two dimensional views with various regions having depth and width, it should be clearly understood that these regions are illustrations of only a portion of a device that is actually a three-dimensional structure. Accordingly, these regions will have three dimensions, including length, width, and depth, when fabricated on an actual device. Moreover, while the present disclosure is illustrated by embodiments directed to active devices, it is not intended that these illustrations be a limitation on the scope or applicability of the present disclosure. It is not intended that the active devices of the present disclosure be limited to the physical structures illustrated. These structures are included to demonstrate the utility and application of the present disclosure to presently preferred embodiments. [0011] It is noted that terms such as top, bottom, over, above, and under may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or elem