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EP-4736596-A1 - STACKED NANOSHEET FETS WITH GATE DIELECTRIC FILL

EP4736596A1EP 4736596 A1EP4736596 A1EP 4736596A1EP-4736596-A1

Abstract

A semiconductor cell comprises a top FET (106) that contains a first set of silicon nanosheets (114A-114D) and a bottom FET (102) that contains a second set of silicon nanosheets (110A, 110B). The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill (118) within the top FET cutout region.

Inventors

  • SENAPATI, BISWANATH
  • Khan, Shahrukh
  • BAJPAI, Utkarsh
  • HOOK, Terence, Blackwell
  • ZHANG, CHEN
  • WANG, JUNLI

Assignees

  • International Business Machines Corporation

Dates

Publication Date
20260506
Application Date
20240524

Claims (20)

  1. 1 . A semiconductor cell comprising: a top field effect transistor (FET) that contains a first set of silicon nanosheets; a bottom FET that contains a second set of silicon nanosheets, wherein the top FET and bottom FET are in a stacked profile; a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets; and a dielectric fill within the top FET cutout region.
  2. 2. The semiconductor cell of claim 1 , further comprising: a top-FET gate material in the top FET; and a gate cap formed on the gate material and the dielectric fill.
  3. 3. The semiconductor cell of claim 1 or claim 2, further comprising: a top-FET gate material in the top FET, wherein the top-FET gate material is formed between the dielectric fill and the first set of silicon nanosheets and upon a top surface of the dielectric fill.
  4. 4. The semiconductor cell of any preceding claim, further comprising a gate sidewall that is in the top FET cutout region and between the dielectric fill and the first set of silicon nanosheets.
  5. 5. The semiconductor cell of any preceding claim, further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets, wherein the dielectric fill extends to the middle dielectric isolation layer.
  6. 6. The semiconductor cell of any preceding claim, further comprising: a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets; and a gate material between the dielectric fill and the middle dielectric isolation layer.
  7. 7. The semiconductor cell of any preceding claim, further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets, wherein the dielectric fill and the middle dielectric isolation layer are composed of a same material.
  8. 8. A set of semiconductor cells, the set of semiconductor cells comprising the semiconductor cell of claim 1 .
  9. 9. The set of semiconductor cells of claim 8, comprising: a second semiconductor cell with a second top FET cutout region, wherein a second dielectric fill is formed within the second top FET cutout region.
  10. 10. A set of semiconductor cells, the set of semiconductor cells comprising: a first semiconductor cell with a first top FET cutout region, wherein a first dielectric fill is formed within the first top FET cutout region; and a second semiconductor cell with a second top FET cutout region, wherein a second dielectric fill is formed within the second top FET cutout region.
  11. 11 . The set of semiconductor cells of claim 10, wherein the first dielectric fill and the second dielectric fill are the same dielectric fill.
  12. 12. The set of semiconductor cells of claim 11, further comprising a gate cap formed upon a top surface of the dielectric fill, wherein the gate cap spans the width of the first semiconductor cell and the second semiconductor cell.
  13. 13. The set of semiconductor cells of any of claims 10 to 12, further comprising a gate cut through between the first dielectric fill and the second dielectric fill.
  14. 14. The set of semiconductor cells of any of claims 10 to 13, further comprising: a third semiconductor cell located horizontally with respect to the first semiconductor cell from a cross- gate-cut view perspective, wherein the third semiconductor cell comprises a third top FET cutout region, and wherein a third dielectric fill is formed within the third top FET cutout region.
  15. 15. A semiconductor cell in a set of semiconductor cells, the semiconductor cell comprising: a top field effect transistor (FET) that contains a first set of silicon nanosheets; a bottom FET that contains a second set of silicon nanosheets, wherein the top FET and bottom FET are in a stacked profile; a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets; and a dielectric fill within the top FET cutout region.
  16. 16. The semiconductor cell of claim 15, further comprising: a top-FET gate material in the top FET; and a gate cap formed on the gate material and the dielectric fill.
  17. 17. The semiconductor cell of claim 15 or claim 16, further comprising: a top-FET gate material in the top FET, wherein the top-FET gate material is formed between the dielectric fill and the first set of silicon nanosheets and upon a top surface of the dielectric fill.
  18. 18. The semiconductor cell of any of claims 15 to 17, further comprising a gate sidewall that is in the top FET cutout region and between the dielectric fill and the first set of silicon nanosheets.
  19. 19. The semiconductor cell of any of claims 15 to 18, further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets, wherein the dielectric fill extends to the middle dielectric isolation layer.
  20. 20. The semiconductor cell of any of claims 15 to 19, further comprising: a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets; and a gate material between the dielectric fill and the middle dielectric isolation layer.

Description

STACKED NANOSHEET FETS WITH GATE DIELECTRIC FILL BACKGROUND [0001] The present invention relates to nanosheet field effect transistors, and more specifically, to stacked nanosheet field effect transistors. [0002] Nanosheet field effect transistors are a type of field effect transistor (FET) in which a set of parallel semiconductor sheets (referred to herein as "nanosheets”) are patterned such that they are layered over each other. The set of nanosheets is typically surrounded on each side by gate material (sometimes referred to as "work function metal”) that can be used to switch the state of the FET. Each nanosheet in the set is typically also separated from each other nanosheet by gate material. As a result, each nanosheet in a typical nanosheet FET has high contact area to the FET gate, causing the performance of the FET to be higher than previous FET designs (e.g., planar FETs). [0003] In a stacked nanosheet cell design, two complementary nanosheet FETs are patterned over each other in the same dimension in which the nanosheets within each FET are patterned over each other. These two FETs are typically referred to as a "top FET” and a "bottom FET” based on their positions relative to the silicon substrate on which the nanosheet cell is formed. Specifically, the FET that is closer to the silicon substrate is typically referred to as the "bottom FET,” and the FET that is farther from the silicon substrate is typically referred to as the "top FET.” [0004] Stacked nanosheet cell designs permit increased cell density, and corresponding performance increases, even beyond the advances resulting from the standard nanosheet FET design. However, each FET in the stacked cell typically requires a contact spanning from the top of the cell (i.e., opposite of the silicon substrate) to the diffusion regions (i.e., source or drain). Thus, in the typical stacked nanosheet cell design, the contact for the bottom FET diffusion regions passes through the top FET. This often requires that the nanosheet cell is formed in a stepped profile, in which the nanosheets of the top FET are not as wide as the nanosheets in the bottom FET. This provides an area through which the contact for the bottom-FET diffusion regions can travel. This area is often referred to herein as the top FET cutout region. [0005] However, in the typical stacked FET design, the space to the left and right of the set of nanosheets is filled by gate material. Because the nanosheets in the top FET of a nanosheet cell are narrower than the nanosheets in the bottom FET of the nanosheet cell, the top FET of the cell is typically surrounded by more gate material than the bottom FET. In other words, the top FET cutout region is filled only with gate material, whereas the corresponding area of the bottom FET contains semiconductor nanosheets and diffusion regions. [0006] Further, because the gate is composed of work function metal, the gate surrounding the FETs has a high capacitance. Thus, filling the top FET cutout region in the top FET with a large mass of gate material can cause a significant amount of parasitic capacitance at the top FET, reducing the switching speed of the top FET. Further, the excess gate material in the top FET cutout region can create capacitance between the top FET gate and the contact for the bottom FET diffusion regions, reducing the switching speed of the bottom FET as well. In some use cases, this parasitic capacitance can be significant enough to not only affect the performance of the FETs in the cell, but also the FETs of adjacent stacks. SUMMARY [0007] Some embodiments of the present disclosure can be illustrated as a semiconductor cell. The semiconductor cell comprises a top field effect transistor (FET) that contains a first set of silicon nanosheets. The semiconductor cell also comprises a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell also comprises a top FET cutout region that is lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region. [0008] Some embodiments of the present disclosure can also be illustrated as a semiconductor cell in a set of semiconductor cells. The semiconductor cell comprises a top field effect transistor (FET) that contains a first set of silicon nanosheets. The semiconductor cell also comprises a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell also comprises a top FET cutout region that is lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region. [0009] Some embodiments of the present disclosure can also be illustrated as a set of semiconductor cells. The set of semiconductor cells co