EP-4736597-A1 - STACKED TRANSISTORS WITH DIELECTRIC INSULATOR LAYERS

Abstract

A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.

Inventors

• XIE, RUILONG
• FROUGIER, JULIEN
• REBOH, SHAY
• YAMASHITA, TENKO

Assignees

• International Business Machines Corporation

Dates

Publication Date

20260506

Application Date

20240604

Claims (20)

1. 1 . A semiconductor structure, comprising: a first stacked device comprising: a first field-effect transistor comprising one or more first nanosheet layers; a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width; and a second stacked device adjacent the first stacked device, the second stacked device comprising: a third field-effect transistor comprising one or more third nanosheet layers; a fourth field-effect transistor vertically stacked above the third field-effect transistor, the fourth field-effect transistor comprising one or more fourth nanosheet layers; and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor, the second dielectric insulator layer having a second width less than the first width of the first dielectric insulator layer.
2. 2 The semiconductor structure according to claim 1 , wherein the first width of the first dielectric insulator layer is equal to a third width of the one or more second nanosheet layers, and the second width of the second dielectric insulator layer is equal to a fourth width of the one or more third nanosheet layers.
3. 3 The semiconductor structure according to claim 1 or claim 2, further comprising a third dielectric insulator layer disposed on a bottom surface of the first stacked device and a fourth dielectric insulator layer disposed on a bottom surface of the second stacked device.
4. 4 The semiconductor structure according to any preceding claim, wherein the first stacked device and the second stacked device are separated by an isolation dielectric pillar.
5. 5 The semiconductor structure according to any preceding claim, wherein the first field-effect transistor further comprises a first gate structure and the second field-effect transistor further comprise a second gate structure separated from the first gate structure by the first dielectric insulator layer.
6. 6 The semiconductor structure according to claim 5, further comprising a first frontside gate contact connected to the first gate structure and a frontside back-end-of-the-line layer.
7. 7. The semiconductor structure according to claim 6, further comprising a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer.
8. 8. The semiconductor structure according to any preceding claim, wherein the second stacked device further comprises a third gate structure disposed over the third field-effect transistor and the fourth field-effect transistor.
9. 9 The semiconductor structure according to claim 8, further comprising a second frontside gate contact connected to the third gate structure and a frontside back-end-of-the-line layer.
10. 10 A semiconductor structure, comprising: a first stacked device comprising: a first field-effect transistor comprising a first gate structure; a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising a second gate structure; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor and separating the first gate structure from the second gate structure; and a second stacked device adjacent the first stacked device, the second stacked device comprising: a third field-effect transistor; a fourth field-effect transistor vertically stacked above the third field-effect transistor; a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor; and a third gate structure disposed over the third field-effect transistor, the fourth field-effect transistor and the second dielectric insulator layer.
11. 11 The semiconductor structure according to claim 10, wherein the third gate structure is a shared gate structure between the third field-effect transistor and the fourth field-effect transistor.
12. 12 The semiconductor structure according to claim 11, further comprising a first frontside gate contact connected to the third gate structure and a frontside back-end-of-the-line layer.
13. 13 The semiconductor structure according to claim 12, further comprising a second frontside gate contact connected to the first gate structure and the frontside back-end-of-the-line layer.
14. 14 The semiconductor structure according to claim 13, further comprising a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer.
15. 15. The semiconductor structure according to any of claims 10 to 14, wherein the first dielectric insulator layer has a first width and the second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.
16. 16. The semiconductor structure according to any of claims 10 to 15, wherein the first stacked device and the second stacked device are separated by an isolation dielectric pillar.
17. 17. The semiconductor structure according to any of claims 10 to 16, wherein: the first field-effect transistor comprises one or more first nanosheet layers; the second field-effect transistor comprises one or more second nanosheet layers; the third field-effect transistor comprises one or more third nanosheet layers; and the fourth field-effect transistor comprises one or more fourth nanosheet layers.
18. 18. An integrated circuit, comprising: one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises: a first stacked device comprising: a first field-effect transistor comprising a first gate structure; a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising a second gate structure; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor and separating the first gate structure from the second gate structure; and a second stacked device adjacent the first stacked device, the second stacked device comprising: a third field-effect transistor; a fourth field-effect transistor vertically stacked above the third field-effect transistor; a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor; and a third gate structure disposed over the third field-effect transistor, the fourth field-effect transistor and the second dielectric insulator layer.
19. 19. The integrated circuit according to claim 18, wherein the at least one of the one or more semiconductor structures further comprises a first frontside gate contact connected to the third gate structure and a frontside back-end- of-the-line layer.
20. 20. The integrated circuit according to claim 19, wherein the at least one of the one or more semiconductor structures further comprises a second frontside gate contact connected to the first gate structure and the frontside back- end-of-the-line layer, and a backside gate contact connected to the second gate structure and a backside back-end-of- the-line layer.

Description

STACKED TRANSISTORS WITH DIELECTRIC INSULATOR LAYERS BACKGROUND [0001] A field-effect transistor (FET) is a transistor having a source, a gate, and a drain, the operation of which depends on the flow of carriers (electrons or holes) along a channel that runs between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate. FETs are widely used for switching, amplification, filtering, and other tasks. SUMMARY [0002] Illustrative embodiments of the present disclosure include techniques for use in semiconductor manufacture. In an illustrative embodiment, a semiconductor structure comprises a first stacked device comprising a first field-effect transistor comprising one or more first nanosheet layers, a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising one or more second nanosheet layers, and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further comprises a second stacked device adjacent the first stacked device. The second stacked device comprises a third field-effect transistor comprising one or more third nanosheet layers, a fourth field-effect transistor vertically stacked above the third field-effect transistor, the fourth field-effect transistor comprising one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer. [0003] The semiconductor structure of the illustrative embodiment advantageously allows for forming a first dielectric insulator layer of a first stacked device having a different width than a second dielectric insulator layer of a second stacked device adjacent the first stacked device resulting in both shared gate integration and independent gate devices. [0004] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the first width of the first dielectric insulator layer is equal to a third width of the one or more second nanosheet layers, and the second width of the second dielectric insulator layer is equal to a fourth width of the one or more third nanosheet layers. [0005] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises a third dielectric insulator layer disposed on a bottom surface of the first stacked device and a fourth dielectric insulator layer disposed on a bottom surface of the second stacked device. [0006] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the first stacked device and the second stacked device are separated by an isolation dielectric pillar. [0007] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the first field-effect transistor further comprises a first gate structure and the second field-effect transistor further comprise a second gate structure separated from the first gate structure by the first dielectric insulator layer. [0008] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises a first frontside gate contact connected to the first gate structure and a frontside back-end-of-the-line layer. [0009] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer. [0010] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the second stacked device further comprises a third gate structure disposed over the third field-effect transistor and the fourth field-effect transistor. [0011] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the semiconductor structure further comprises a second frontside gate contact connected to the third gate structure and a frontside back-end-of-the-line layer. [0012] In another illustrative embodiment, a semiconductor structure comprises a first stacked device structure comprising a first field-effect transistor disposed comprising a first source/drain region, and a second fieldeffect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor comprising a second source/drain region. The first stacked device further comprises a frontside source/drain contact disposed on a first portion of a sidewal