EP-4736598-A1 - INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENTIAL EPITAXIAL SOURCE OR DRAIN DENT

Abstract

Integrated circuit structures having differential epitaxial source or drain dent are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. A second sub-fin structure is beneath a second stack of nanowires or fin. A first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.

Inventors

• GHOSH, SWAPNADIP
• HUANG, CHIAO-TI
• RAI, Amritesh
• Matsubayashi, Akitomo
• KHAN, Fariha
• BOWONDER, ANUPAMA
• PATEL, REKEN
• CHOI, CHI-HING

Assignees

• INTEL Corporation

Dates

Publication Date

20260506

Application Date

20231026

Claims (20)

1. 1. An integrated circuit structure, comprising: a first sub-fin structure beneath a first stack of nanowires; a second sub-fin structure beneath a second stack of nanowires; a first epitaxial source or drain structure at an end of the first stack of nanowires, the first epitaxial source or drain structure having no dent or a shallower dent therein; and a second epitaxial source or drain structure at an end of the second stack of nanowires, the second epitaxial source or drain structure having a deeper dent therein.
2. 2. The integrated circuit structure of claim 1, wherein the shallower dent is less than 5% of a vertical thickness of the first epitaxial source or drain structure, and wherein the deeper dent is greater than 10% of a vertical thickness of the second epitaxial source or drain structure.
3. 3. The integrated circuit structure of claim 1 or 2, wherein the deeper dent has a saddle shape.
4. 4. The integrated circuit structure of claim 1, 2 or 3, wherein the first epitaxial source or drain structure is a P-type epitaxial source or drain structure, and the second epitaxial source or drain structure is an N-type epitaxial source or drain structure.
5. 5. The integrated circuit structure of claim 1, 2, 3 or 4, further comprising: a first trench contact structure on the first epitaxial source or drain structure; and a second trench contact structure on the second epitaxial source or drain structure, the second trench contact structure having a vertical thickness greater than a vertical thickness of the first trench contact structure.
6. 6. An integrated circuit structure, comprising: a first sub-fin structure beneath a first fin; a second sub-fin structure beneath a second fin; a first epitaxial source or drain structure at an end of the first fin, the first epitaxial source or drain structure having no dent or a shallower dent therein; and a second epitaxial source or drain structure at an end of the second fin, the second epitaxial source or drain structure having a deeper dent therein.
7. 7. The integrated circuit structure of claim 6, wherein the shallower dent is less than 5% of a vertical thickness of the first epitaxial source or drain structure, and wherein the deeper dent is greater than 10% of a vertical thickness of the second epitaxial source or drain structure.
8. 8. The integrated circuit structure of claim 6 or 7, wherein the deeper dent has a saddle shape.
9. 9. The integrated circuit structure of claim 6. 7 or 8, wherein the first epitaxial source or drain structure is a P-type epitaxial source or drain structure, and the second epitaxial source or drain structure is an N-type epitaxial source or drain structure.
10. 10. The integrated circuit structure of claim 6, 7, 8 or 9, further comprising: a first trench contact structure on the first epitaxial source or drain structure; and a second trench contact structure on the second epitaxial source or drain structure, the second trench contact structure having a vertical thickness greater than a vertical thickness of the first trench contact structure.
11. 11. A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a first sub-fin structure beneath a first stack of nanowires or a first fin; a second sub-fin structure beneath a second stack of nanowires or a second fin; a first epitaxial source or drain structure at an end of the first stack of nanowires of the first fin, the first epitaxial source or drain structure having no dent or a shallower dent therein; and a second epitaxial source or drain structure at an end of the second stack of nanowires or the second fin, the second epitaxial source or drain structure having a deeper dent therein.
12. 12. The computing device of claim 11, comprising the first and second stacks of nanowires.
13. 13. The computing device of claim 11. comprising the first and second fins.
14. 14. The computing device of claim 11, 12 or 13, further comprising: a memory coupled to the board.
15. 15. The computing device of claim 11, 12, 13 or 14, further comprising: a communication chip coupled to the board.
16. 16. The computing device of claim 11. 12. 13. 14 or 15. further comprising: a battery coupled to the board.
17. 17. The computing device of claim 11, 12, 13, 14, 15 or 16, further comprising: a camera coupled to the board.
18. 18. The computing device of claim 11. 12. 13, 14, 15, 16 or 17, further comprising: a display coupled to the board.
19. 19. The computing device of claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.
20. 20. The computing device of claim 11. 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Description

INTEGRATED CIRCUIT STRUCTURES WITH DIFFERENTIAL EPITAXIAL SOURCE OR DRAIN DENT TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, integrated circuit structures having differential epitaxial source or drain dent, and methods of fabricating integrated circuit structures having differential epitaxial source or drain dent. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A-1B illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having differential epitaxial source or drain dent, in accordance with an embodiment of the present disclosure. Figure 1C illustrates cross-sectional views representing an integrated circuit structure having differential epitaxial source or drain dent, in accordance with an embodiment of the present disclosure. Figure ID illustrates cross-sectional views representing another integrated circuit structure having differential epitaxial source or drain dent, in accordance with another embodiment of the present disclosure. Figures 2A-2I illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a backside trench contact cut, in accordance with an embodiment of the present disclosure. Figure 3 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. Figures 4A-4H illustrate plan views of a substrate processed with double-sided device processing methods, in accordance with some embodiments. Figures 5A-5H illustrate cross-sectional views of a substrate processed with double-sided device processing methods, in accordance with some embodiments. Figure 6 illustrates a cross-sectional view taken through nanowires and fins for a nonendcap architecture, in accordance with an embodiment of the present disclosure. Figure 7 illustrates a cross-sectional view taken through nanowires and fins for a selfaligned gate endcap (SAGE) architecture, in accordance with an embodiment of the present disclosure. Figure 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure. Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 8A, as taken along the a-a’ axis, in accordance with an embodiment of the present disclosure. Figure 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of Figure 8A, as taken along the b-b’ axis, in accordance with an embodiment of the present disclosure. Figure 9 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure. [0001] Figure 10 illustrates an interposer that includes one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS Integrated circuit structures having differential epitaxial source or drain dent, and methods of fab