Search

EP-4736599-A1 - INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL-TRANSPORT TRANSISTOR WITH BOTTOM SOURCE CONNECTION

EP4736599A1EP 4736599 A1EP4736599 A1EP 4736599A1EP-4736599-A1

Abstract

Structures having vertical-transport field effect transistors (FETs) with bottom source connection are described. In an example, an integrated circuit structure includes a channel structure above a substrate. A gate structure is laterally surrounding the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically beneath the channel structure. A conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.

Inventors

  • GEIGER, RICHARD
  • BAUMGARTNER, PETER

Assignees

  • INTEL Corporation

Dates

Publication Date
20260506
Application Date
20231030

Claims (20)

  1. 1. An integrated circuit structure, comprising: a channel structure above a substrate; a gate structure laterally surrounding the channel structure; a drain structure above the gate structure and on the channel structure; a metal source structure below the substrate and vertically beneath the channel structure; and a conductive via through the substrate, the conductive via coupling the metal source structure to the channel structure.
  2. 2. The integrated circuit structure of claim 1, wherein the channel structure comprises a vertical fin array.
  3. 3. The integrated circuit structure of claim 1 or 2, wherein the substrate comprises a silicon- on-insulator structure.
  4. 4. The integrated circuit structure of claim 1, 2 or 3, further comprising one or more trench isolation structures in the substrate and laterally adjacent to the conductive via.
  5. 5. The integrated circuit structure of claim 1, 2, 3 or 4, wherein the metal source structure has a lateral width greater than a lateral width of the drain structure.
  6. 6. An integrated circuit structure, comprising: a front side structure comprising: a device layer having a plurality of vertical transport field effect transistors (FETs); and a plurality of metallization layers above the vertical transport FETs of the device layer; and a backside structure below the vertical transport FETs of the device layer, the backside structure including a ground metal line or a power metal line.
  7. 7. The integrated circuit structure of claim 6, wherein each of the vertical transport FETs comprises a vertical fin array.
  8. 8. The integrated circuit structure of claim 6 or 7, wherein each of the vertical transport FETs comprises a metal source structure vertically beneath a channel structure.
  9. 9. The integrated circuit structure of claim 8, wherein each of the vertical transport FETs comprises a conductive via between the metal source structure and the channel structure.
  10. 10. The integrated circuit structure of claim 6 or 7. wherein each of the vertical transport FETs comprises a buried power rail.
  11. 11. A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a channel structure above a substrate; a gate structure laterally surrounding the channel structure; a drain structure above the gate structure and on the channel structure; a metal source structure below the substrate and vertically beneath the channel structure; and a conductive via through the substrate, the conductive via coupling the metal source structure to the channel structure.
  12. 12. The computing device of claim 11. further comprising: a memory coupled to the board.
  13. 13. The computing device of claim 1 1 or 12, further comprising: a communication chip coupled to the board.
  14. 14. The computing device of claim 11, 12 or 13, further comprising: a camera coupled to the board.
  15. 15. The computing device of claim 11. 12. 13 or 14, further comprising: a battery coupled to the board.
  16. 16. The computing device of claim 11, 12, 13, 14 or 15, further comprising: a speaker coupled to the board.
  17. 17. The computing device of claim 11, 12, 13, 14, 15 or 16, further comprising: a compass coupled to the board.
  18. 18. The computing device of claim 11. 12. 13. 14. 15, 16 or 17, further comprising: a GPS coupled to the board.
  19. 19. The computing device of claim 11, 12, 13, 14, 15, 16, 17 or 18, further comprising: a display coupled to the board.
  20. 20. The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.

Description

INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAE-TRANSPORT TRANSISTOR WITH BOTTOM SOURCE CONNECTION TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, integrated circuit structures having vertical-transport field effect transistors (FETs) with bottom source connection, and methods of fabricating integrated circuit structures having vertical -transport field effect transistors (FETs) with bottom source connection. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity’. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Nanowires used to fabricate devices provide improved short channel control. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. Another aspect driving innovation is the drive for high bandwidth (HBW) computing. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 illustrates cross-sectional views of an interconnect stack having front side power delivery and of an interconnect stack having backside power delivery, in accordance with an embodiment of the present disclosure. Figure 2A illustrates a cross-sectional view of an integrated circuit structure having a nanowire layer and backside power delivery, in accordance with an embodiment of the present disclosure. Figure 2B illustrates an angled view of a vertical-transport field effect transistor (FET). Figure 2C illustrates an angled view of a lateral-transport field effect transistor (FET). Figure 2D illustrates a cross-sectional view of a vertical transport field effect transistor (FET). Figure 2E illustrates a cross-sectional view of a vertical-transport field effect transistor (FET), in accordance with an embodiment of the present disclosure. Figure 2F illustrates a cross-sectional view of another vertical-transport field effect transistor (FET), in accordance with another embodiment of the present disclosure. Figure 2G illustrates a cross-sectional view of another vertical-transport field effect transistor (FET), in accordance with another embodiment of the present disclosure. Figure 3 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. Figures 4A-4H illustrate plan views of a substrate processed with double-sided device processing methods, in accordance with some embodiments. Figures 5A-5H illustrate cross-sectional views of a substrate processed with double-sided device processing methods, in accordance with some embodiments. Figure 6 illustrates a cross-sectional view taken through nanowires and fins for a nonendcap architecture, in accordance with an embodiment of the present disclosure. Figure 7 illustrates a cross-sectional view taken through nanowires and fins for a selfaligned gate endcap (SAGE) architecture, in accordance with an embodiment of the present disclosure. Figure 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure. Figure 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 8A, as taken along the a-a’ axis, in accordance with an embodiment of the present disclosure