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EP-4737960-A1 - METHOD OF MANUFACTURING A PHOTONIC INTEGRATED CIRCUIT (PIC) COMPRISING A LITHIUM NIOBATE WAVEGUIDE

EP4737960A1EP 4737960 A1EP4737960 A1EP 4737960A1EP-4737960-A1

Abstract

Method of manufacturing a photonic integrated circuit with at least one lithium niobate waveguide comprising the following steps : i) providing a lithium niobate-on-insulator (LNOI) stacking, said stacking comprising a silicon (Si) substrate, a first silicon dioxide (SiOz) layer, a lithium niobate (LiNbO 3 ) layer, and a cladding dielectric layer, wherein said lithium niobate layer comprises said lithium niobate waveguide, ii) applying a first photoresist mask on said cladding dielectric layer and creating at least one opening in said first photoresist mask by a photolithography process, iii) implementing a first etching step by Reactive-ion etching (RIE) through said at least one opening, thereby creating at least one cavity across all the thickness of said cladding dielectric layer, said lithium niobate layer and said first silicon dioxide layer, iv) implementing a second etching step by Deep Reactive-ion etching (DRIE) through at least part of said at least one opening, whereby at least part of said at least one cavity is extended further through the silicon substrate along a predetermined depth of at least 100 micrometres.

Inventors

  • GHADIMI, Amir
  • SATTARI, Hamed
  • PRIETO GONZALEZ, IVAN
  • CHOONG, Gregory

Assignees

  • CSEM Centre Suisse d'Electronique et de Microtechnique SA - Recherche et Développement

Dates

Publication Date
20260506
Application Date
20241029

Claims (17)

  1. Method of manufacturing a photonic integrated circuit (100) with at least one lithium niobate waveguide (40) comprising the following steps : i) providing a lithium niobate-on-insulator (LNOI) stacking, said stacking comprising a silicon (Si) substrate (10), a first silicon dioxide (SiO 2 ) layer (12) on said silicon substrate (10), a lithium niobate (LiNbO 3 ) layer (14) on said first silicon dioxide layer (12), and a cladding dielectric layer (16) on said lithium niobate layer (14), wherein said lithium niobate layer (14) comprises said lithium niobate waveguide (40), ii) applying a first photoresist mask (21) on said cladding dielectric layer (16) and creating at least one opening (22) in said first photoresist mask (21) by a photolithography process, iii) implementing a first etching step by Reactive-ion etching (RIE) through said at least one opening (22), thereby creating at least one cavity (23) across all the thickness of said cladding dielectric layer (16), said lithium niobate layer (14) and said first silicon dioxide layer (12), iv) implementing a second etching step by Deep Reactive-ion etching (DRIE) through at least part of said at least one opening (22), whereby at least part of said at least one cavity (23) is extended further through the silicon substrate (10) along a predetermined depth of at least 100 micrometres, forming thereby at least one deeper cavity (24).
  2. Method according to claim 1, wherein said at least one deeper cavity (24) extends through a predetermined depth corresponding to at least one third, preferably at least half of the silicon substrate (10) thickness.
  3. Method according to any of the preceding claims, wherein said at least one deeper cavity (24) comprises a trench in the form of a closed loop which defines a contour of the photonic integrated circuit (100).
  4. Method according to claim 3, further comprising the following step: vii) grinding the bottom side of the silicon substrate (10), which is opposite to the side where the first silicon dioxide layer (12), the lithium niobate layer (14) and the cladding layer (16) are provided, until the thickness of said silicon substrate (10) is reduced down, to reach a value which is equal to or smaller than said predetermined depth, so as to open the bottom of at least said trench in the form of a closed loop, thereby disconnecting said photonic integrated circuit (100) from said lithium niobate-on-insulator (LNOI) stacking.
  5. Method according to any of the preceding claims, further comprising the following steps to be executed after the first etching step iii) and before the second etching step iv): iiia) applying a second photoresist mask (21') on said first photoresist mask (21), whereby said second photoresist mask (21') fills said cavities (23), and iiib) creating at least one new opening (22') through said first and second photoresist masks (21, 21'), which is aligned with but smaller in width than a corresponding opening (22) among said openings (22) previously made in the first photoresist mask (21).
  6. Method according to any of the preceding claims, further comprising the following steps to be executed after the second etching step iv), and before a possible step vii) of grinding the bottom side of the silicon substrate (10): v) removing all photoresist masks (21, 21') and v_a) applying a third etching step, comprising an isotropic etching process.
  7. Method according to any of the preceding claims, comprising creating at least one cavity (23) which is narrow enough to prevent the corresponding deeper cavity (24) from reaching said predetermined depth during the execution of said second etching step, thereby creating a deeper cavity of a second type (242) characterized by a depth which is lower than said predetermined depth and which is dependent on the width of the cavity (23).
  8. Method according to claim 7 wherein said deeper cavity of a second type (242) presents a width which is equal or smaller than one twentieth (1/20) of said predetermined depth.
  9. Method according to any of the previous claims, wherein said at least one cavity (23) realized through said first etching step, also extends into the silicon.
  10. Photonic integrated circuit (100) fabricated by a method according to any of the claims 1 to 9.
  11. Photonic integrated circuit (100) according to claim 10, wherein said at least one deeper cavity (24) has the form of a trench running along one side of at least one portion of a lithium niobate waveguide (40) of said photonic integrated circuit (100).
  12. Photonic integrated circuit (100) according to claim 11, further comprising another deeper cavity (24) in the form of a trench running along the opposite side of said at least one portion of said lithium niobate waveguide (40), such that said portion is partially isolated from the surrounding materials by laying on a ridge (11) of the silicon substrate (10) defined by said trenches.
  13. Photonic integrated circuit (100) according to claim 12, wherein the width of said ridge (11) is between 2 and 200 micrometres.
  14. Photonic integrated circuit (100) according to any of the claims 11 to 13, wherein said at least one deeper cavity(24) having the form of a trench is a deeper cavity of the second type (242) fabricated by a method according to any of the claims 7 or 8 and having a width between 2 and 20 micrometres.
  15. Photonic integrated circuit (100) according to any of claims 10 to 14, wherein it is fabricated by a method including step vii) of claim 4, and wherein it is built such that it has a contour configured to define a mechanical guide for connecting the photonic integrated circuit (100) to another device.
  16. Photonic integrated circuit (100) according to any of claims 10 to 15, wherein it is fabricated by a method according to claims 4 and 5, and wherein the lateral faces of said cladding dielectric layer (16), said lithium niobate layer (14) and said a first silicon dioxide layer (12) are aligned and define a recess (24d) with respect to the lateral walls (30) of the silicon substrate (10').
  17. Photonic integrated circuit (100) according to any of claims 10 to 15, wherein it is fabricated by a method according to claim 6, and wherein the lateral faces of said cladding dielectric layer (16), said lithium niobate layer (14) and said a first silicon dioxide layer (12) are aligned and define a protrusion (24c) with respect to the lateral walls (30) of the silicon substrate (10').

Description

Technical domain The present invention concerns a method of manufacturing a photonic integrated circuit (PIC) with at least one lithium niobate waveguide. More in details, the method of the present invention comprises steps enabling the fabrication of smooth and vertical flanks or deep trenches in such photonic integrated circuits. Related art Lithium niobate has attracted much attention since the 1970s due to its capacity to modify the light by means of an electric control as well as for its great transparency across a broad spectral band. Electro-optical (EO) lithium niobate waveguides have evolved throughout the years, in a race towards ever smaller electro-optical components with ever-lower optical losses and power consumption. Among others, the challenge consists in strongly confining the light while preserving low losses. The use of lithium niobate (LiNbO3) as main photonic material in the field of photonic integrated circuits (PICs) enables miniaturization while possibly designing complex PICs with tens of components in millimetre-sized chips. Those photonic integrated circuits are based on the so-called lithium niobate-on-insulator (LNOI) technology. According to the usual architecture, a substrate made from silicon, is covered by an oxide layer, usually a silicon dioxide layer (SiO2), on which extends a thin lithium niobate film (LiNbO3) patterned to define the waveguides and electro-active components. The stacking may further comprise a cladding layer to protect the waveguides, as well as metallic elements to transmit the electric signals for active electro-optical PICs. This type of PICs are often called "thin-film lithium niobate photonic integrated circuits" (TFLN PICs) Several challenges are encountered when implementing TFLN PICs. Among those challenges, there is a need for providing smooth and vertically oriented walls. In this context "vertical" refers to a direction perpendicular to the planes defined by the layers of the LNOI stacking. It is particularly challenging to implement a process guaranteeing an adequate alignment between the vertical cut planes of the different dielectric layers of the stacking and the vertical cut plane of the silicon substrate. Smooth and vertical walls are necessary for allowing tight connections between different components (e.g. other PICs or optical fibres). The objective is to avoid gaps and angles at the interfaces, which result in major optical losses in the connections between components. Gaps and angles at the interfaces may further result in wobbly connections, sensitive to mechanical perturbations and producing unstable losses, which must also be avoided. Besides the connecting interface application, the capability to define deep vertical narrow trenches in a TFLN PIC is an enabler of new functional features including optical mode confinement, electromagnetic isolation and/or thermal isolation of the waveguides as will be later explained in several examples. Those requirements should be reached without too many additional steps and too much complexity during the manufacturing process. Short disclosure of the invention An aim of the present invention is the provision of a method of manufacturing a photonic integrated circuit with at least one lithium niobate waveguide that overcomes the shortcomings and limitations of the state of the art. According to the invention, this aim is attained by the object of the attached claims 1 to 9, and especially by a method of manufacturing a photonic integrated circuit with at least one lithium niobate waveguide comprising the following steps : i) providing a lithium niobate-on-insulator (LNOI) stacking, said stacking comprising a silicon (Si) substrate, a first silicon dioxide (SiO2) layer on said silicon substrate, a lithium niobate (LiNbO3) layer on said first silicon dioxide layer, and a cladding dielectric layer on said lithium niobate layer, wherein said lithium niobate layer comprises said lithium niobate waveguide,ii) applying a first photoresist mask on said cladding dielectric layer and creating at least one opening in said first photoresist mask by a photolithography process,iii) implementing a first etching step by Reactive-ion etching (RIE) through said at least one opening, thereby creating at least one cavity across all the thickness of said cladding dielectric layer, said lithium niobate layer, and said first silicon dioxide layer,iv) implementing a second etching step by Deep Reactive-ion etching (DRIE) through at least part of said at least one opening, whereby at least part of said at least one cavity is extended further through the silicon substrate down to a predetermined depth of at least 100 micrometres, forming thereby at least one deeper cavity. With respect to what is known in the art, the invention provides the advantage that it is possible to manufacture in a simple way deep cavities passing through an important depth of the silicon substrate, and which provide smooth and clean vertical