EP-4737965-A2 - PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURE

Abstract

Photonic packages and device assemblies that include photonic integrated circuits (PICs) are described. An example integrated circuit (IC) device assembly comprises: a circuit board; a photonic package above the circuit board and a coupling structure between the circuit board and a second surface of a package support. The photonic package comprises: the package support having a first surface and the second surface opposite the first surface; a photonic integrated circuit (PIC) die over a first portion of the second surface of the package support; a processor die over a second portion of the second surface of the package support; a first electronic integrated circuit (EIC) die coupled in a flip-chip configuration with the PIC die; a second EIC die coupled in a flip-chip configuration with the PIC die; an optical coupler at a lateral surface of the PIC die; an adhesive between the optical coupler and the lateral surface of the PIC die; and a heat sink. Each of the PIC die and the processor die is between the package support and the heat sink.

Inventors

• KARHADE, OMKAR G.
• LI, Xiaoqian
• IBRAHIM, Tarek A.
• MAHAJAN, Ravindranath Vithal
• DESHPANDE, NITIN A.

Assignees

• INTEL Corporation

Dates

Publication Date

20260506

Application Date

20220322

Claims (17)

1. An integrated circuit, IC, device assembly, comprising: a circuit board; a photonic package above the circuit board, comprising: a package support having a first surface and a second surface opposite the first surface; a photonic integrated circuit, PIC, die over a first portion of the second surface of the package support, wherein the PIC die includes a waveguide, an optical modulator, a photodetector, and a phase shifter; a processor die over a second portion of the second surface of the package support; a first electronic integrated circuit, EIC, die coupled in a flip-chip configuration with the PIC die, the first EIC die comprising an optical modulator driver; a second EIC die coupled in a flip-chip configuration with the PIC die, the second EIC die comprising a transimpedance amplifier, TIA; an optical coupler at a lateral surface of the PIC die; an adhesive between the optical coupler and the lateral surface of the PIC die; and a heat sink, wherein each of the PIC die and the processor die is between the package support and the heat sink; and a coupling structure between the circuit board and the second surface of the package support.
2. The IC device assembly of claim 1, wherein the first EIC die is between the package support and the PIC die.
3. The IC device assembly of claim 1 or 2, wherein the second EIC die is between the package support and the PIC die.
4. The IC device assembly of any one of claims 1 to 3, wherein the lateral surface of the PIC die intersects with a base surface of the PIC die.
5. The IC device assembly of claim 4, wherein the lateral surface of the PIC die is perpendicular to the base surface of the PIC die.
6. The IC device assembly of claim 4 or 5, wherein: the lateral surface of the PIC die is one of four lateral surfaces of the PIC die, the base surface of the PIC die is one of two base surfaces of the PIC die, and a surface area of the two base surfaces of the PIC die is larger than a surface area of the four lateral surfaces of the PIC die.
7. The IC device assembly of claim 6, wherein the two base surfaces of the PIC die are opposite one another.
8. The IC device assembly of any one of claims 1 to 7, wherein the waveguide is a silicon-on-insulator waveguide.
9. The IC device assembly of any one of claims 1 to 8, wherein the PIC die includes a silicon substrate and a layer of an insulator material on the silicon substrate.
10. The IC device assembly of claim 9, wherein the waveguide is a silicon waveguide, and wherein the layer of the insulator material is between the silicon substrate and the silicon waveguide.
11. The IC device assembly of any one of claims 1 or 10, wherein the first EIC die overlaps with the PIC die along one or more edges.
12. The IC device assembly of any one of claims 1 to 11, wherein a footprint of the first EIC die at least partially overlaps with a footprint of the PIC die.
13. The IC device assembly of any one of claims 1 to 12, wherein the second EIC die overlaps with the PIC die along one or more edges.
14. The IC device assembly of any one of claims 1 to 13, wherein a footprint of the second EIC die at least partially overlaps with a footprint of the PIC die.
15. The IC device assembly of any one of claims 1 to 14, wherein the PIC die is to support wavelengths between 800 nanometers and 1700 nanometers.
16. The IC device assembly of any one of claims 1 to 15, further comprising a die-to-die, DTD, interconnect between the first EIC die and the PIC die.
17. The IC device assembly of claim 16, wherein the DTD interconnect is a pillar or a copper pillar.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of and priority to U.S. Non-Provisional Application No. 17/237,375, filed 22 April 2021, entitled PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURE, the disclosure of which is hereby incorporated by reference in its entirety for all purposes. TECHNICAL FIELD The present disclosure relates to packaging photonic integrated circuits (PICs). More specifically, it relates to techniques, methods, and apparatus directed to PIC packaging architecture. BACKGROUND Contemporary optical communications and other systems often employ PICs. Smaller, faster, and less expensive optical components can enable universal, low-cost, high-volume optical communications needed for fast and efficient communication technologies demanded by high volume internet data traffic. In optical communications, information is transmitted by way of an optical carrier whose frequency typically is in the visible or near-infrared region of the electromagnetic spectrum. A carrier with such a high frequency is sometimes referred to as an optical signal, an optical carrier, a light wave signal, or simply light. A typical optical communications network includes several optical fibers, each of which may include several channels. A channel is a specified frequency band of an electromagnetic signal and is sometimes referred to as a wavelength. Technological advances today enable implementing portions of optical communication systems at the integrated circuit (IC) (or chip or die) level in PICs. Packaging such PICs presents many challenges. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. FIG. 1A is a schematic cross-sectional view of an example photonic packaging architecture, according to some embodiments of the present disclosure.FIG. 1B is a schematic illustration of an example detail of a photonic package, according to some embodiments of the present disclosure.FIGS. 1C-1F are schematic cross-sectional views of example details of a photonic package according to various embodiments of the present disclosure.FIG. 2 is a schematic cross-sectional view of another example photonic packaging architecture, according to some embodiments of the present disclosure.FIG. 3 is a schematic cross-sectional view of yet another example photonic packaging architecture, according to some embodiments of the present disclosure.FIGS. 4A-4H are schematic cross-sectional illustrations of various stages in an example process to fabricate a photonic package, according to some embodiments of the present disclosure.FIGS. 5A-5H are schematic cross-sectional illustrations of various stages in another example process to fabricate a photonic package, according to some embodiments of the present disclosure.FIGS. 6A-6I are schematic cross-sectional illustrations of various stages in yet another example process to fabricate a photonic package, according to some embodiments of the present disclosure.FIGS. 7A-7J are schematic cross-sectional illustrations of various stages in yet another example process to fabricate a photonic package, according to some embodiments of the present disclosure.FIG. 8 is a flow diagram of an example method of fabricating a photonic package, according to various embodiments of the present disclosure.FIG. 9 is a flow diagram of another example method of fabricating a photonic package, according to various embodiments of the present disclosure.FIG. 10 is a cross-sectional view of a device package that may include one or more photonic packages in accordance with any of the embodiments disclosed herein.FIG. 11 is a cross-sectional side view of a device assembly that may include one or more photonic packages in accordance with any of the embodiments disclosed herein.FIG. 12 is a block diagram of an example computing device that may include one or more photonic packages in accordance with any of the embodiments disclosed herein. DETAILED DESCRIPTION Overview For purposes of illustrating photonic packages described herein, it is important to understand phenomena that may come into play during packaging of PICs. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications. In a general sense, a PIC integrates photonic functions for information signals imposed on electromagnetic waves, e.g., electromagnetic waves of optical wavelengths. PICs find application in fiber-optic communication, medical, security, sensing, and ph