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EP-4738097-A1 - DRIVING ASSEMBLY, METHOD AND SYSTEM FOR MULTI-PERIOD MODULATION, AND PRODUCT

EP4738097A1EP 4738097 A1EP4738097 A1EP 4738097A1EP-4738097-A1

Abstract

The present invention presents a driving component, method, system, and product for multi-period modulation. Utilizing for example SDN technology to decouple the control plane from the hardware, the remote controller may realize the data configuration of storage units and programming of circuit logic devices of different devices based on the controlled device code, provide multiple periodic/non-periodic timing driving signals required by a variety of device chips, and be compatible with the timing requirements of the driving and data readout of different device chip arrays. The driving component for multi-period modulation includes a state division component, a synchronization multi-period configuration component and a single-period modulation component. The state division component is used for functional decoding according to the function mode of the device, and generating timing-matched trigger signals according to the specific function mode; the synchronous multi-period configuration component is used to generate multiple types of periodic/non-periodic enable signals at different main frequencies according to the configuration information, so as to realize multi-period timing driving; the single-period modulation component may be used as a general modulation unit, and each unit may generate periodic composite on-chip timing driving signals according to the configuration information and multi-period driving signal, thereby meeting the driving needs of digital and analog readout units of different device chips. The proposed invention can greatly simplify the overall timing structure of the driving chip, through the use of programmable interconnected sub-module arrays which are generated in software, the remote controller may realize output of the multi-period modulation driving signal in batch, without additional customized design to meet the flexible configuration and real-time switching needs of periodic and non-periodic driving signals by the different devices in multiple modes. This reduces design complexity, and each module subunit may be configured off-chip with individual timing, which improves the fault tolerance and flexibility of chip timing design, while the reusability of multiple modules shortens the design period.

Inventors

  • SUN, Yanwen
  • WANG, Wenzhu

Assignees

  • Nanjing VPS Semiconductor Technology Co., Ltd.

Dates

Publication Date
20260506
Application Date
20240905

Claims (6)

  1. A driving component for multi-period modulation for generating multi-period driving signals for a plurality of controlled devices at a back-end, characterized in that the driving component comprises a state division component, a synchronization multi-period configuration component and a single-period modulation component connected in sequence; and (1) the state division component configured to: modulate request information for startup of the controlled device to satisfy synchronous trigger or asynchronous trigger requirements of a timing; the state division component comprising a mode judgement logic module ModeJudge_Logic and a trigger delay module TriggerDelay and adapted to at least one digital input signal and one digital output signal for functional decoding according to a function mode of the controlled device, and generating a timing-matched trigger signal according to the function mode of the controlled device; wherein the at least one digital input signal is data configuration information Config_Data1, which comprises working mode information of the driving component and configuration parameters in different function modes, wherein the working mode information of the driving component comprises request information TriggerBegin requesting the controlled device to start up, and the configuration parameters in different function modes comprise at least one of duration of a reset state, duration of an exposure state, duration of a readout state, and duration of a program state; the at least one digital output signal is a timing-matched trigger signal MatchTriggerBegin transmitted to the synchronization multi-period configuration component; and the mode judgement logic module ModeJudge_Logic configured to make a combinatorial logic judgment and configure a delay storage unit (MatchNum) based on data configuration information Config_Data1; the trigger delay module TriggerDelay configured to realize modulation of delay time of a period enable driving signal and a trigger signal from the outside in different function modes based on configuration information of delay storage unit (MatchNum) and the request information TriggerBegin, and output the trigger signal MatchTriggerBegin which meets timing requirements to the synchronization multi-period configuration component; (2) the synchronous multi-period configuration component configured to: generate multi-period/non-period driving enable signals based on the configuration information and the trigger signal at working clock frequencies of different controlled devices; the synchronous multi-period configuration component configured to be adapted to at least two digital input signals and at least two digital output signals for generating multiple types of periodic/non-periodic enable signals based on off-chip configuration information, and simultaneously implementing multi-period timing driving on-chip; wherein the at least two digital input signals are the trigger signal MatchTriggerBegin from the state division component and data configuration information Config_Data2 from off-chip, respectively, and the at least two digital output signals are a set of driving enable signal PeriodValid and end signal ModeEnd capable of characterizing a multiple of period types of the chip; wherein the synchronization multi-period configuration component comprises a decoding module, k clock reset generation sub-modules, and k configuration sub-modules, wherein the decoding module decodes and outputs data obtained from decoding to the k clock reset generation sub-modules and k configuration sub-modules based on the data configuration information Config_Data2, in order to perform data configuration and selection on at least one sub-module of the k clock reset generation sub-modules and k configuration sub-modules; each sub-module of the k clock reset generation sub-modules and k configuration sub-modules is configured to generate different periodic/non-periodic driving enable signal PeriodValid based on off-chip configuration information to realize multi-period enable modulation under the same clock frequency group, wherein k is a number of driving enable signals to be generated, k is a positive integer; the synchronization multi-period configuration component makes a combinational logic judgment and configures corresponding enable signal period storage unit (PeriodNum), high level duration storage unit in a single period (EnableNum) and a single-period repetition number storage unit (RepeatNum) based on data configuration information Config_Data2, realizes timing configuration of periodic and/or non-periodic driving signals by means of counters PeriodCounter and RepeatCounter, and outputs multi-period driving enable signal PeriodValid and end signal ModeEnd for a single-period modulation component, and (3) the single-period modulation component configured to: modulate and output a composite driving signal required by the controlled device chip based on the configuration information and a driving enable signal; the single-period modulation component adapted to at least four digital input signals and at least one digital output signal; the single-period modulation component generates a periodic composite on-chip timing driving signal to drive a digital and analog readout unit in the controlled device chip based on off-chip signal type code and configuration information as well as the multi-period driving enable signal PeriodValid and end signal ModeEnd; the four digital input signals are signal type code Config_Type, timing data configuration information Config_Data3 for a corresponding signal, a driving enable signal PeriodValid and an end signal ModeEnd, and the one digital output signal is a complex on-chip timing driving signal DriverSignal required by the digital and analog readout unit in the controlled device chip; and, the single-period modulation component comprises n driving sub-modules responsible for generation of a plurality of complex on-chip timing driving signals, wherein n is a number of driving signals to be generated and n is a positive integer; and each driving sub-module of the n driving sub-modules comprises a state machine sub-module and a selector, determines type of the driving signal and flip number of high and low levels through combinational logic based on input signal type code Config_Type, generates an on-chip timing driving signal DriverSignal through modulation of state machine sub-module based on an input driving enable signal PeriodValid; based on device code DeviceType in the input timing data configuration information, output of on-chip timing driving signal DriverSignal or output of driving enable signal PeriodValid is realized through the selector.
  2. The driving component for multi-period modulation as claimed in claim 1, characterized in that , the digital input signal of the state division component further comprises request information TriggerBegin requesting the controlled device to start up, and an end signal ModeEnd; the TriggerBegin information is the request information for startup of the controlled device, and the state division component, after receiving the TriggerBegin information, carries out modulation based on data configuration information Config_Data1 to meet synchronous trigger or asynchronous trigger requirements of working timing of the controlled device chip; the end signal ModeEnd is an end signal of working mode of the controlled device, and is fed back to the state division component and output to the single-period modulation component to carry out a clear (Clear) operation on storage unit within state division component and single-period modulation component and to turn off the output driving signal.
  3. The driving component for multi-period modulation as claimed in claim 1 or 2, characterized in that the storage unit is a register.
  4. A driving system for multi-period modulation comprising a plurality of composite periodic processes in operation, characterized in that the driving system comprises the driving component for multi-period modulation as claimed in claim 1 or 2 for generating multi-period driving signals for a plurality of controlled devices controlled by the driving system.
  5. A driving method for multi-period modulation, characterized in that a state division component, a synchronization multi-period configuration component and a single-period modulation component which are connected in sequence are adopted, the state division component comprising a mode judgment logic module and a trigger delay module, and the driving method comprises following steps: S1, performing function state division: after the state division component receives data configuration information Config_Data1 containing working mode code of the controlled device, corresponding function mode timing and data configuration, the mode judgment logic module is configured to configure a delay storage unit based on the data configuration information Config_Data1, and a delay value in the delay storage unit is denoted as a MatchNum; the trigger delay module is configured to start working upon triggering by a trigger signal based on request message TriggerBegin requesting the controlled device to start up in configuration information Config_Data1 from the outside, and when its built-in counter counts up to MatchNum, it outputs a timing-matched trigger signal MatchTriggerBegin, duration of high level of the MatchTriggerBegin being greater than a predetermined value to enable the synchronized triggering process to proceed normally, S2, performing configuration of a multi-period enable signal, the synchronization multi-period configuration component, after receiving data configuration information Config _Data2 of the controlled device, performs a combinational logic judgment and configures an enable signal period storage unit, a high level duration storage unit in a single period, and a single-period repetition number storage unit, wherein a value configured in the enable signal period storage unit is denoted as PeriodNum, a value configured in the high level duration storage unit in the single-period is denoted as EnableNum, and a value configured in the single-period repetition number storage unit is denoted as RepeatNum; k sub-modules exemplified by the synchronization multi-period configuration component start to work after receiving the timing-matched trigger signal MatchTriggerBegin, the counter PeriodCounter starts counting, and outputs an enable signal PeriodValid with duration of a single period which isPeriodNum and duration of a high level in a single period which is EnableNum; after counting a single period repetition number of the enable signal to EnableNum, the counter RepeatCounter outputs the end signal ModeEnd, in order to simultaneously realize multi-period driving enable for subsequent k single-period modulation sub-modules in the chip, S3, performing generation of a modulation signal within a single period; after receiving off-chip configuration information Config_Type and Config_Data3, the single-period modulation component determines type and timing information of driving signal by a combinational logic, and configures corresponding storage units; the n sub-modules exemplified by the single-period modulation component operate under same driving enable signal PeriodValid and operate when the driving enable signal PeriodValid is at a high level, and built-in counter and sub-state machine modulate PeriodValid into an n periodic composite on-chip timing driving signal DriverSignal, in order to realize timing driving of digital and analog readout unit of the controlled device chip.
  6. A computer program product comprising a computer program characterized in that the computer program when executed by a processor implements a driving method as described in claim 5.

Description

TECHNICAL FIELD The present invention proposes a driving component, a driving method, a driving system, and a product for multi-period modulation, which belongs to the field of digital integrated circuits. BACKGROUND As for a current device chip with complicated functions, there is an inevitable driving need for the multi-period complex timing. This makes a high requirement for the timing docking between a front module and a rear module in the hardware circuit, and as for the mode which needs a work flow, the timing will be more complex; therefore, it is often necessary to design a complex driving circuit for multi-period timing, used as a driving for the digital and analog readout in sequential rows and columns, so as to meet the driving and readout requirements for the device chip with complicated functions. Currently the mainstream driving and readout circuit design solution for the device chip employs a top-down design method, that is, first planning the top-level timing requirements, and then based on the timing designing the front and rear circuits. The solution needs to first determine the array driving circuit and readout circuit hardware structure of the overall chip and then design the timing, and finally design the control logic to generate the timing. The circuit usually uses a complex counter module, and outputs the driving signal which meets the driving needs of the chip through the off-chip triggering of the work signal and timing configuration information. This solution has a complex on-chip circuit design, a large area, and a long design period, which is often customized for special driving needs. Timing adjustments are all fine-tuning of the state duration, which cannot change the overall driving timing, and the waveform has a low degree of adjustable flexibility, and the manpower and docking costs of subsequent verification are very high. SUMMARY The present invention proposes a driving component, a driving method, a driving system, and a product for multi-period modulation, which decouples a control plane from the hardware by utilizing for example Software-Defined Networking (SDN) technology, so that a remote controller may realize data configuration of storage units and programming of circuit logic devices for different controlled devices based on a device code, and provide a variety of periodic/non-periodic timing driving signals required by multiple types of controlled device chips, which is compatible with the timing requirements of the array driving and data readout of different device chips. Using the programmable interconnected sub-module arrays which are generated in software, the remote controller may realize the output of multi-period modulation driving signals in batch, without any additional individual customized design for meeting the needs of flexible configuration and real-time switching for periodic and non-periodic driving signals of different devices in multiple modes, so as to reduce the complexity of the design and costs of design and validation, and to realize the flexible configuration of driving signals in multiple modes of multiple devices. The driving component, driving method, driving system and product also provide driving solutions for current satellite device programming and cloud device control on the basis of meeting the driving requirements of different device chips. By converting digital driving signals into control signals, the microprocessors and microcontrollers of different devices may drive various functions of electronic devices, such as controlling mechanical movements, processing data, and managing communications. The technical solution adopted for the circuit of the present invention is as follows: A driving component for multi-period modulation and a driving method thereof, characterized in that a control plane is separated from a hardware using for example SDN technology, and a logically centralized remote controller is used to configure parameters of a numerical control circuit for a multi-period modulation driving based on device code information through a communication data interface between the control level and a hardware level implemented by for example a protocol such as OpenFlow. The driving component also feeds data back to a controller side in real time via a data feedback link, enabling a flexible and efficient configuration of the hardware circuits. The programmable interconnected sub-module array circuit which is generated in software includes a state division component, a synchronization multi-period configuration component, and a single-period modulation component connected in sequence; the state division component is used to functionally decode according to a function mode, and generate a trigger signal that meets timing requirements based on a specific function mode; the synchronization multi-period configuration component is used to generate multiple types of periodic/non-periodic enable signals at different main frequencies o