EP-4738131-A1 - SYSTEMS AND METHODS FOR ADDRESS TRANSLATION IN SWITCH APPARATUSES

EP4738131A1EP 4738131 A1EP4738131 A1EP 4738131A1EP-4738131-A1

Abstract

The subject technology is directed to a switch apparatus for address translation in data communication systems. In an embodiment, the switch apparatus includes a first port configured to receive a first request associated with a first address and a cache configured to store a plurality of mapping entries. The switch apparatus further includes a routing unit coupled to the cache, configured to determine the presence or absence of a second address associated with the first address in the cache. The cache allows for efficient storage and retrieval of frequently used address translations, reducing the need to repeatedly access the host system for address translations. This minimizes latency in handling data requests and improves overall system performance. By retrieving address translations from the cache, the system can optimize data flow and enhance the speed and efficiency of data communication across multiple devices. There are other embodiments as well.

Inventors

Khaparde, Ajit Kumar

Assignees

Avago Technologies International Sales Pte. Limited

Dates

Publication Date: 20260506
Application Date: 20251022

Claims (13)

A switch apparatus comprising: a first port configured to receive a first request associated with a first address; a cache configured to store a plurality of mapping entries; a routing unit coupled to the cache, the routing unit being configured to: determine a presence or an absence of a second address in the plurality of mapping entries, the second address being associated with the first address; in response to a determination of the presence of the second address in the plurality of mapping entries, retrieve the second address; and in response to a determination of the absence of the second address in the plurality of mapping entries, forward the first request to a first device to obtain the second address; and a second port coupled to the routing unit, the second port being configured to transmit the first request based on the second address; wherein the routing unit is configured to update the cache with a first mapping entry associating the first address with the second address obtained from the first device.
The apparatus of claim 1, wherein the first device is configured to provide the second address by performing an address translation based on the first address.
The apparatus of claim 1 or 2, further comprising a buffer coupled to the routing unit, the buffer being configured to store the first request.
The apparatus of any one of the claims 1 to 3, further comprising a controller coupled to the cache, the controller being configured to manage the plurality of mapping entries stored in the cache based on a predetermined criterion.
The apparatus of claim 4, wherein the predetermined criterion comprises at least one of an access frequency, a storage duration, or a cache capacity.
The apparatus of any one of the claims 1 to 5, wherein the first address comprises a virtual address.
The apparatus of any one of the claims 1 to 6, wherein the second address comprises a physical address.
The apparatus of any one of the claims 1 to 7, wherein the first request comprises a direct memory access (DMA) request.
The apparatus of any one of the claims 1 to 8, wherein the first device comprises an upstream component.
The apparatus of claim 9, wherein the upstream component comprises a second switch or a host.
A switch apparatus comprising: a first port configured to receive a first request associated with a first address; a cache configured to store a plurality of mapping entries, the plurality of mapping entries comprising a first mapping entry associating the first address with a second address; a controller coupled to the cache, the controller being configured to manage the plurality of mapping entries stored in the cache based on a predetermined criterion; a routing unit coupled to the cache, the routing unit being configured to determine a destination for the first request based on the second address; and a second port coupled to the routing unit, the second port being configured to transmit the first request to the destination.
The apparatus of claim 11, wherein the predetermined criterion comprises at least one of an access frequency, a storage duration, or a cache capacity.
The apparatus of claim 11 or 12, wherein the first address comprises a virtual address and the second address comprises a physical address.

Description

BACKGROUND OF THE INVENTION In modern computing and networking environments, reliable and efficient communication between devices is important for maintaining system performance and uptime. Many systems involve multiple devices, such as network interface cards (NICs), storage devices, and processing units, that work together to handle high-volume data traffic. These devices may be interconnected through switches, which manage data routing between devices and external systems, including host systems and other endpoints. Some approaches for data transfer between devices rely on direct memory access (DMA), which allows devices to access memory directly without burdening the central processing unit (CPU). This improves overall efficiency by reducing processing overhead and enabling faster data transfers. For instance, peripheral component interconnect express (PCIe) is a standard that supports high-speed communication between devices, such as NICs, processing units, and storage controllers. PCIe enables direct connections between devices via a bus structure, facilitating efficient data flow between multiple endpoints through switches. As systems become more complex, especially with high-performance workloads such as artificial intelligence (Al) and machine learning (ML), the efficiency of address translation and data routing becomes increasingly important. Devices generating data requests, such as those involving DMA, often use virtual addresses, which must be translated into physical addresses before the data can be routed to its destination. In various implementations, the address translation may be handled by mechanisms such as input/output memory management units (IOMMUs). However, frequent address translations can introduce delays, especially when the same address translations are requested repeatedly, impacting overall system performance. Various approaches for performing address translation in complex systems have been explored, but they have proven to be insufficient. It is important to recognize the need for new and improved systems and methods. BRIEF DESCRIPTION OF THE DRAWINGS A further understanding of the nature and advantages of particular embodiments may be realized by reference to the remaining portions of the specification and the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components. Figure 1 is a schematic diagram illustrating an architecture of a computing system with an address translation service (ATS) mechanism, in accordance with various embodiments of the subject technology.Figure 2 is a schematic diagram illustrating an architecture of a computing system that supports direct memory access (DMA), in accordance with various embodiments of the subject technology.Figure 3 is a schematic diagram illustrating a hierarchical PCIe switch system with integrated address translation cache (ATC), in accordance with various embodiments of the subject technology.Figure 4 is a schematic diagram illustrating a switch apparatus, in accordance with various embodiments of the subject technology.Figure 5 is a schematic diagram illustrating switch mappings and configuration of a computing system, in accordance with various embodiments of the subject technology. DETAILED DESCRIPTION OF THE INVENTION The subject technology is directed to a switch apparatus for address translation in data communication systems. In an embodiment, the switch apparatus includes a first port configured to receive a first request associated with a first address and a cache configured to store a plurality of mapping entries. The switch apparatus further includes a routing unit coupled to the cache, configured to determine the presence or absence of a second address associated with the first address in the cache. The cache allows for efficient storage and retrieval of frequently used address translations, reducing the need to repeatedly access the host system for address translations. This minimizes latency in handling data requests and improves overall system performance. By retrieving address translations from the cache, the system can optimize data flow and enhance the speed and efficiency of data communication across multiple devices. There are other embodiments as well. One general aspect includes a switch apparatus, which comprises: a first port configured to receive a first request associated with a first address; a cache configured to store a plurality of mapping entries; a routing unit coupled to the cache. The routing unit is configured to: determine a presence or an absence of a second address in the plurality of mapping entries, the second address being associated with the first address; in response to a determination of t