EP-4738133-A1 - MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY SYSTEM

EP4738133A1EP 4738133 A1EP4738133 A1EP 4738133A1EP-4738133-A1

Abstract

There is provided a memory device including a memory controller with reduced power consumption. The memory device includes a first volatile memory (112) including a first logical memory device (MLD1) and a CXL memory controller (111) that controls operations of the first volatile memory (112) and receive requests for the first volatile memory (112) from a host (101) through a CXL interface (CXL_IF) including a CXL switch (103). The CXL memory controller (111) includes a coarse-grained global counter (120) configured to count a number of requests received store a count value, a global hotness monitor (121) configured to determine, based on respective ones of the count values, whether each memory unit is a hot unit or a cold unit, a hotness tracker controller (130) configured to generate a first bitmap and a first hotness tracker configured to determine, based on the first bitmap, whether data stored in each of the plurality of segments included in the first logical memory device (MLD1) is hot.

Inventors

LEE, WON JAE
NAM, HO JIN
SO, Jin In

Assignees

Samsung Electronics Co., Ltd.

Dates

Publication Date: 20260506
Application Date: 20250403

Claims (15)

A memory device comprising: a first volatile memory (112) including a first logical memory device (MLD1) ; and a CXL memory controller (111) configured to control operations of the first volatile memory (112) and receive requests for the first volatile memory (112) from a host (101) through a CXL interface (CXL_IF) including a CXL switch (103), wherein the first logical memory device (MLD1) includes a plurality of segments (Seg1-Seg4c) that are physically separated from one another, wherein at least two of the plurality of segments (Seg1-Seg4c) form a single memory unit among a plurality of memory units (Unit1-Unit4) of the first logical memory device (MLD1), and wherein the CXL memory controller (111) comprises: a coarse-grained global counter (120) configured to count a number of the requests received for each of the plurality of memory units (Unit1-Unit4) of the first logical memory device (MLD1) and store count values respectively associated with the number of the requests received for each of the plurality of memory units (Unit1-Unit4); a global hotness monitor (121) configured to determine, based on respective ones of the count values, whether each of the plurality of memory units (Unit1-Unit4) of the first logical memory device (MLD1) is a hot unit or a cold unit; a hotness tracker controller (130) configured to generate a first bitmap for each of the plurality of memory units (Unit1-Unit4) of the first logical memory device (MLD1) based on results of a determination of the global hotness monitor (121); and a first hotness tracker (140_1) configured to determine, based on the first bitmap, whether data stored in each of the plurality of segments (Seg1-Seg4c) included in the first logical memory device (MLD1) is hot.
The memory device of claim 1, wherein in response to a determination that first data stored in a first segment among the plurality of segments (Seg1-Seg4c) is hot based on the first bitmap, the first hotness tracker (140_1) is configured to store the first data in a second volatile memory (102a, 102b) of the host (101), and wherein the host (101) and the second volatile memory (102a, 102b) are not connected to each other through the CXL interface (CXL_IF).
The memory device of claim 2, wherein the host (101) and the second volatile memory (102a, 102b) are configured to communicate with each other through a Double Data Rate, DDR, interface.
The memory device of any one of claims 1 to 3, wherein the hotness tracker controller (130) comprises a power management module (133) configured to manage power supplied to the first hotness tracker (140_1), and wherein in response to the global hotness monitor (121) determining that all of the plurality of memory units (Unit1-Unit4) included in the first logical memory device (MLD1) are cold units, the power management module (133) is configured to cut off the power supplied to the first hotness tracker (140_1).
The memory device of any one of claims 1 to 4, wherein the hotness tracker controller (130) comprises a filtering module (132), and wherein in response to a first memory unit among the plurality of memory units (Unit1-Unit4) included in the first logical memory device (MLD1) being determined to be a cold unit, the filtering module (132) is configured to clear bits in the first bitmap corresponding to ones of the plurality of segments included in the first memory unit.
The memory device of claim 5, wherein in response to the bits in the first bitmap corresponding to the ones of the plurality of segments included in the first memory unit being cleared, the first hotness tracker (140_1) is configured to not determine whether the data stored in each of the plurality of segments included in the first memory unit is hot.
The memory device of any one of claims 1 to 4, wherein the plurality of memory units (Unit1-Unit4) includes a first memory unit and a second memory unit having different physical addresses, wherein the global hotness monitor (121) is configured to determine the first memory unit as a cold unit if a first count value of the count values for the first memory unit is less than a cold threshold value, and is configured to determine the second memory unit as a hot unit if a second count value of the count values for the second memory unit exceeds a hot threshold value, and wherein the cold threshold value and the hot threshold value are preset by the host (101).
The memory device of any one of claims 1 to 4, wherein the plurality of memory units (Unit1-Unit4) includes a first memory unit that includes a first segment and a second segment having different physical addresses, wherein the first hotness tracker (140_1) is configured to determine data stored in the first and second segments as hot if requests for the first memory unit exceed a hot threshold value per epoch, wherein the hotness tracker controller (130) includes a sampling module (131), and wherein the sampling module (131) is configured to sample some of the requests for the first memory unit during a subsequent epoch and transmits the requests that have been sampled to the first hotness tracker (140_1) in response to the global hotness monitor (121) determining the first memory unit as a hot unit.
The memory device of claim 8, wherein the hot threshold value is preset by the host (101).
The memory device of any one of claims 1 to 4, wherein the plurality of memory units (Unit1-Unit4) includes a first memory unit determined to be a hot unit by the global hotness monitor (121), and wherein the hotness tracker controller (130) is configured to transmit requests received for the first memory unit to the first hotness tracker (140_1).
The memory device of claim 10, wherein the first hotness tracker (140_1) is configured to count a number of the received requests and is configured to determine whether data stored in each of the plurality of segments included in the first memory unit is hot.
The memory device of claim 10 or 11, wherein the first memory unit includes a first segment and a second segment of the plurality of segments, wherein the hotness tracker controller (130) includes a sampling module (131), and wherein the sampling module (131) is configured to transmit some of requests received per epoch for the first memory unit to the first hotness tracker (140_1) in response to a number of the requests that were received exceeding a hot threshold value set by the host (101).
The memory device of any one of claims 1 to 12, wherein the first volatile memory (112) further comprises a second logical memory device (MLD2), wherein the second logical memory device (MLD2) includes ones of the plurality of segments that are physically separated from one another, wherein at least two of the plurality of segments included in the second logical memory device (MLD2) form a single memory unit among a plurality of memory units (Unit1', Unit2', Unit3', Unit4') of the second logical memory device (MLD2), wherein the coarse-grained global counter (120) is configured to count a number of the requests received for each of the plurality of memory units (Unit1', Unit2', Unit3', Unit4') of the second logical memory device (MLD2) and store count values respectively associated with the number of the requests received for each memory unit of the second logical memory device (MLD2), wherein the global hotness monitor (121) is configured to determine, based on the count values for the second logical memory device (MLD2), whether each of the plurality of memory units (Unit1', Unit2', Unit3', Unit4') of the second logical memory device (MLD2) is a hot unit or a cold unit, wherein the hotness tracker controller (130) is configured to generate a second bitmap for each of the plurality of memory units (Unit1', Unit2', Unit3', Unit4') of the second logical memory device (MLD2) based on results of a determination of the global hotness monitor (121) for the second logical memory device (MLD2), and wherein the CXL memory controller (111) further includes a second hotness tracker configured to determine, based on the second bitmap, whether data stored in each of the plurality of segments included in the second logical memory device (MLD2) is hot.
A memory system comprising: a host (101); a first CXL memory device including a first volatile memory (112) that includes a first logical memory device (MLD1), and a first CXL memory controller (111) that is configured to control operations of the first volatile memory (112); and a CXL switch (103) configured to provide an interface between the host (101)and the first CXL memory device, wherein the host (101) is configured to transmit first requests for the first volatile memory (112) through the CXL switch (103), wherein the first logical memory device (MLD1) includes a plurality of segments that are physically separated from one another, wherein at least two of the plurality of segments form a single memory unit among a plurality of memory units (Unit1, Unit2, Unit3, Unit4) of the first logical memory device (MLD1), wherein the CXL switch (103) comprises: a coarse-grained global counter (120a) configured to count a number of the first requests received for each of the plurality of memory units (Unit1, Unit2, Unit3, Unit4) of the first logical memory device (MLD1) and store count values respectively associated with the number of the first requests received for each of the plurality of memory units (Unit1, Unit2, Unit3, Unit4); a global hotness monitor (121a) configured to determine, based on respective ones of the count values, whether each of the plurality of memory units (Unit1, Unit2, Unit3, Unit4) of the first logical memory device (MLD1) is a hot unit or a cold unit; and a hotness tracker controller (130a) configured to generate a first bitmap for each of the plurality of memory units (Unit1, Unit2, Unit3, Unit4) of the first logical memory device (MLD1) based on results of the determination of the global hotness monitor (121a), and wherein the first CXL memory controller (111) is configured to determine, based on the first bitmap, whether data stored in each of the plurality of segments included in the first logical memory device (MLD1) is hot, using a first hotness tracker.
The memory system of claim 14, wherein the memory system further comprises: a second CXL memory device (110_K) including a second volatile memory (112_K) that includes a second logical memory device; and a second CXL memory controller (111_K) configured to control operations of the second volatile memory, wherein the CXL switch (103) is further configured to provide an interface between the host (101) and the second CXL memory device (110_K), wherein the host (101) is configured to transmit second requests for the second volatile memory through the CXL switch (103), wherein the second logical memory device includes a plurality of segments that are physically separated from one another, wherein at least two of the plurality of segments included in the second logical memory device form a single memory unit among a plurality of memory units of the second logical memory device, wherein the coarse-grained global counter (120a) is configured to count a number of the second requests received for each of the plurality of memory units of the second logical memory device and store count values respectively associated with the number of the second requests received for each of the plurality of memory units of the second logical memory device, wherein the global hotness monitor (121a) is configured to determine, based on respective ones of the count values for the second logical memory device, whether each of the plurality of memory units of the second logical memory device is a hot unit or a cold unit, wherein the hotness tracker controller (130a) is configured to generate a second bitmap for each of the plurality of memory units of the second logical memory device based on results of the determination of the global hotness monitor (121a) for the second logical memory device, and wherein the second CXL memory controller (111_K) is configured to determine, based on the second bitmap, whether data stored in each of the plurality of segments included in the second logical memory device is hot, using a second hotness tracker.

Description

BACKGROUND The present disclosure relates to a memory device, a memory system including the memory device, and an operating method of the memory system. With advancements in technologies such as artificial intelligence (AI), big data, and edge computing, there is a growing demand for devices to process larger amounts of data more quickly. That is, high-bandwidth applications performing complex computations require faster data processing and more efficient memory access. However, host devices, including computational devices such as CPUs and GPUs, are mostly connected to semiconductor devices containing memory via the PCIe protocol. As a result, they face limitations such as relatively low bandwidth, high latency, and issues related to memory sharing and consistency with the semiconductor devices. To address these limitations, the Compute Express Link (CXL) interface, which provides a low-latency and high-bandwidth link, is being utilized. Meanwhile, when data stored in a CXL memory device communicating with a host via the CXL interface is frequently accessed by the host, a feature called CXL memory hotness tracking can be provided to migrate such data to the double data rate (DDR) memory of the host. SUMMARY A technical problem to be solved by the present disclosure is to provide a memory device including a memory controller with reduced power consumption. Another technical problem to be solved by the present disclosure is to provide a memory system including a memory controller with reduced power consumption. Yet another technical problem to be solved by the present disclosure is to provide an operating method of a memory system including a memory controller with reduced power consumption. However, aspects of the present disclosure are not restricted to those set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below. According to some embodiments of the present disclosure, there is provided a memory device comprising a first volatile memory including a first logical memory device and a CXL memory controller configured to control operations of the first volatile memory and receive requests for the first volatile memory from a host through a CXL interface including a CXL switch, wherein the first logical memory device includes a plurality of segments that are physically separated from one another, at least two of the plurality of segments form a single memory unit among a plurality of memory units of the first logical memory device, and the CXL memory controller includes a coarse-grained global counter configured to count a number of the requests received for each of the plurality of memory units of the first logical memory device and store count values respectively associated with the number of the requests received for each of the plurality of memory units, a global hotness monitor configured to determine, based on respective ones of the count values, whether each of the plurality of memory units of the first logical memory device is a hot unit or a cold unit, a hotness tracker controller configured to generate a first bitmap for each of the plurality of memory units of the first logical memory device based on results of a determination of the global hotness monitor, and a first hotness tracker configured to determine, based on the first bitmap, whether data stored in each of the plurality of segments included in the first logical memory device is hot. According to some embodiments of the present disclosure, there is provided a memory system comprising a host, a first CXL memory device including a first volatile memory that includes a first logical memory device, and a first CXL memory controller that is configured to control operations of the first volatile memory and a CXL switch configured to provide an interface between the host and the first CXL memory device, wherein the host is configured to transmit first requests for the first volatile memory through the CXL switch, the first logical memory device includes a plurality of segments that are physically separated from one another, at least two of the plurality of segments form a single memory unit among a plurality of memory units of the first logical memory device, the CXL switch includes a coarse-grained global counter configured to count a number of the first requests received for each of the plurality of memory units of the first logical memory device and store count values respectively associated with the number of the first requests received for each of the plurality of memory units, a global hotness monitor configured to determine, based on respective ones of the count values, whether each of the plurality of memory units of the first logical memory device is a hot unit or a cold unit, and a hotness tracker controller configured to generate a first bitm