EP-4738134-A1 - SYSTEM AND METHOD FOR LOW-POWER DOUBLE DATA RATE (LPDDR) COMPATIBLE HIGH BANDWIDTH NAND (HBN)

Abstract

Systems and methods for low-power double data rate, LPDDR, compatible High Bandwidth NAND, HBN, include receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via a memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via the memory controller to fulfill the request.

Inventors

• LI, ZONGWANG
• LEE, HO BIN
• YANG, JING
• PITCHUMANI, REKHA
• KI, YANG SEOK
• JUNG, MYUNG JUNE

Assignees

• Samsung Electronics Co., Ltd.

Dates

Publication Date

20260506

Application Date

20251022

Claims (15)

1. A method, comprising: receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via a memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via the memory controller to fulfill the request.
2. The method of claim 1, wherein the memory controller includes a low-power double data rate, LPDDR, memory controller.
3. The method of claim 2, wherein the memory device includes a High Bandwidth Flash NAND memory and a front-end controller configured to control the High Bandwidth Flash NAND memory based on commands from the LPDDR memory controller.
4. The method of any one of claims 1 to 3, wherein the request type is a write request.
5. The method of claim 4, wherein the status of the memory device is based on availability of space in a buffer of the memory device.
6. The method of claim 5, further comprising: reserving an amount of space in the buffer for the application.
7. The method of any one of claims 1 to 3, wherein the request type is a read request.
8. The method of claim 7, wherein the status of the memory device is based on availability of data associated with the request in a buffer of the memory device.
9. A system, comprising: a host comprising: a memory controller; a processing circuit; and memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, causes performance of a method, the method comprising: receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via the memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via the memory controller to fulfill the request.
10. The system of claim 9, wherein the memory controller includes a low-power double data rate, LPDDR, memory controller.
11. The system of claim 10, wherein the memory device includes a High Bandwidth Flash NAND memory and a front-end controller configured to control the High Bandwidth Flash NAND memory based on commands from the LPDDR memory controller.
12. The system of any one of claims 9 to 11, wherein the request type is a write request.
13. The system of claim 12, wherein the status of the memory device is based on availability of space in a buffer of the memory device.
14. The system of claim 13, the method further comprising: reserving an amount of space in the buffer for the application.
15. The system of any one of claims 9 to 11, wherein the request type is a read request.

Description

FIELD One or more aspects of embodiments according to the present disclosure relate to computing systems, and more particularly to a system and method for low-power double data rate compatible High Bandwidth Flash. BACKGROUND Some computing devices such as mobile device may utilize low-power double data rate (LPDDR) SDRAM and are equipped with an LPDDR memory controller. High Bandwidth Flash (HBF) NAND memory devices may have potential to provide higher throughput, but may be incompatible with LPDDR memory controllers. It is with respect to this general technical environment that aspects of the present disclosure are related. OBJECTIVE OF THE DISCLOSURE The object of the present disclosure is to provide a system and method for LPDDR compatible high bandwidth NAND. SUMMARY In one or more embodiments, a method comprises: receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via a memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via the memory controller to fulfill the request. In some embodiments, the memory controller includes a low-power double data rate (LPDDR) memory controller. In some embodiments, the memory device includes a High Bandwidth Flash NAND memory and a front-end controller configured to control the High Bandwidth Flash NAND memory based on commands from the LPDDR memory controller. In some embodiments, the request type is a write request. In some embodiments, the status of the memory device is based on availability of space in a buffer of the memory device. In some embodiments, the method further comprises reserving an amount of space in the buffer for the application. In some embodiments, the request type is a read request. In some embodiments, the status of the memory device is based on availability of data associated with the request in a buffer of the memory device. In one or more embodiments, a system, comprises: a host comprising: a memory controller; a processing circuit; and memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, causes performance of a method, the method comprising: receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via the memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via the memory controller to fulfill the request. In some embodiments, the memory controller includes a low-power double data rate (LPDDR) memory controller. In some embodiments, the memory device includes a High Bandwidth Flash NAND memory and a front-end controller configured to control the High Bandwidth Flash NAND memory based on commands from the LPDDR memory controller. In some embodiments, the request type is associated with a write request. In some embodiments, the status of the memory device is based on availability of space in a buffer of the memory device. In some embodiments, the method further comprising reserving an amount of space in the buffer for the application. In some embodiments, the request type is a read request. In some embodiments, the status of the memory device is based on availability of data associated with the request in a buffer of the memory device. In one or more embodiments, a memory device, comprises: a High Bandwidth NAND (HBN); and a front-end controller configured to control access to the HBN, the front-end controller comprising: a buffer; a processing circuit; and memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, causes performance of a method, the method comprising: receiving a first command from a memory controller of a host device; determining that a status of the buffer satisfies a condition associated with the first command; transmitting the status of the buffer to the memory controller; receiving a second command from the memory controller; and executing an action with respect to the buffer based on the second command. In some embodiments, the second command is a read request for data stored in the HBN, and wherein the condition includes the data being in the buffer. In some embodiments, the second command is a write request for data to be stored in the HBN, and wherein the condition includes the buffer having enough space available for the data. In some embodiments, the method further