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EP-4738137-A2 - OPERATION METHOD OF HOST CONFIGURED TO COMMUNICATE WITH STORAGE DEVICES AND MEMORY DEVICES, AND SYSTEM INCLUDING STORAGE DEVICES AND MEMORY DEVICES

EP4738137A2EP 4738137 A2EP4738137 A2EP 4738137A2EP-4738137-A2

Abstract

A system includes a first compute express link (CXL) storage device, a second CXL storage device, a first CXL memory device, and a CXL switch connected to the first CXL storage device, the second CXL storage device and the first CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device and the second CXL storage device, and the first CXL memory device. The first CXL memory device is configured to store first map data of the first CXL storage device and second map data of the second CXL storage device, the first CXL storage device is configured to exchange at least a portion of the first map data with the first CXL memory device through the CXL switch, and the second CXL storage device is configured to exchange at least a portion of the second map data with the first CXL memory device through the CXL switch.

Inventors

  • LEE, Kyunghan
  • LEE, JAE-GON
  • LEE, CHON YONG

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260506
Application Date
20230503

Claims (14)

  1. A computing system comprising: a compute express link, CXL, switch (SW_CXL); a first CXL storage device (210; 410_1) connected to the CXL switch (SW_CXL), and the first CXL storage device (210; 410_1) being configured to store first user data from an external host and first map data (MD1); a first CXL memory device (220_1; 420_1) connected to the CXL switch (SW_CXL); and a second CXL memory device (220_2; 420_2) connected to the CXL switch (SW_CXL); wherein the first map data (MD1) comprises first sub-map data (MD1-a) and second sub-map data (MD1-b), wherein the first CXL storage device (210; 410_1) is further configured to store the first sub-map data (MD1-a) in the first CXL memory device (220_1; 420_1) and the second sub-map data (MD1-b) in the second CXL memory device (220_2; 420_2), in an initialization operation.
  2. The computing system of claim 1, wherein the first CXL storage device (210; 410_1) comprises a nonvolatile memory configured to store the first map data (MD1) and the first user data, and wherein the first map data (MD1) indicates a relationship between a logical address of the first user data managed by the external host (201; 401) and a physical address of the nonvolatile memory at which the first user data is stored.
  3. The computing system of claim 1 or 2, wherein, in the initialization operation, a first dedicated area of the first CXL memory device (220_1; 420_1) and a second dedicated area of the second CXL memory device (220_2; 420_2) are allocated to the first CXL storage device (210; 410_1).
  4. The computing system of claim 3, wherein the first sub-map data (MD1-a) is stored in the first dedicated area of the first CXL memory device (220_1; 420_1) and the second sub-map data (MD1-b) is stored in the second dedicated area of the second CXL memory device (220_2; 420_2).
  5. The computing system of any one of claims 1 to 4, wherein the first CXL storage device (210; 410_1) communicates with the external host (201; 401) based on a CXL.io protocol being a peripheral component interconnect express (PCIe)-based non-coherency input/output protocol, and the first CXL storage device (210; 410_1) communicates with each of the first and second CXL memory devices (220_1, 220_2; 420_1, 420_2) based on a CXL.mem being a memory access protocol supporting memory access.
  6. The computing system of any one of claims 1 to 5, further comprising a second CXL storage device (410_2) connected to the CXL switch (SW_CXL), and the second CXL storage device (410_2) being configured to store second user data from the external host (401) and second map data (MD2), and wherein the second map data (MD2) comprises third sub-map data and fourth sub-map data.
  7. The computing system of claim 6, wherein the third sub-map data is stored in the first CXL memory device (220_1; 420_1) and the fourth sub-map data is stored in the second CXL memory device (220_2; 420_2).
  8. The computing system of claim 6, further comprising: a third CXL memory device (220_3; 420_3) connected to the CXL switch (SW_CXL); and a fourth CXL memory device (220_4; 420_4) connected to the CXL switch (SW_CXL), wherein the third sub-map data is stored in the third CXL memory (220_3; 420_3) and the fourth sub-map data is stored in the fourth CXL memory device.
  9. The computing system of claim 6, wherein the second CXL storage device (410_2) is further configured to support a hot-plug function installed in or removed from the CXL switch (SW_CXL).
  10. The computing system of claim 6, wherein when a residual region of the first and second CXL memory devices (220_1, 220_2; 420_1, 420_2), in which the first sub-map data (MD1-a) and the second sub-map data (MD1-b) are not stored, is smaller in size than the second map data (MD2) of the second CXL storage device (410_2), the second CXL storage device (410_2) is not identified by the external host as a storage device.
  11. An operation method of a computing system including a first compute express link, CXL, storage device (210; 410_1), a first CXL memory device (220_1; 420_1), a second CXL memory device (220_2; 420_2), and a CXL switch (SW_CXL), the method comprising: transmitting, by the first CXL storage device (210; 410_1), a memory allocation request to an external host (201; 401) through the CXL switch (SW_CXL); receiving, by the first CXL storage device (210; 410_1), a memory allocation response from the external host (201; 401), the memory allocation response including information about the first and second CXL memory devices (220_1, 220_2; 420_1, 420_2) through the CXL switch (SW_CXL); transmitting, by the first CXL storage device (210; 410_1), first sub-map data (MD1-a) of first map data to the first CXL memory device (220_1; 420_1) through the CXL switch (SW_CXL); storing, by the first CXL memory device (220_1; 420_1), the first sub-map data (MD1-a) in a first dedicated area; transmitting, by the first CXL storage device (210; 410_1), second sub-map data (MD1-b) of first map data (MD1) to the second CXL memory device (220_2; 420_2) through the CXL switch (SW_CXL); and storing, by the second CXL memory device (220_2; 420_2), the second sub-map data (MD1-b) in a second dedicated area.
  12. The method of claim 11, wherein the first CXL storage device (210; 410_1) comprises a nonvolatile memory configured to store the first map data (MD1) and the first user data, and wherein the first map data (MD1) indicates a relationship between a logical address of the first user data managed by the external host (201; 401) and a physical address of the nonvolatile memory at which the first user data is stored.
  13. The method of claim 11 or 12, wherein the first dedicated area and the second dedicated area are allocated, by the external host (201; 401), to the first CXL storage device (210; 410_1) in an initialization operation.
  14. The method of any one of claims 11 to 13 further comprises: transmitting, by the first CXL storage device (210; 410_1), first storage device information to the external host (201; 401) through the CXL switch (SW_CXL); transmitting, by the first CXL memory device (220_1; 420_1), first memory device information to the external host (201; 401) through the CXL switch (SW_CXL); and transmitting, by the second CXL memory device (220_2; 420_2), second memory device information to the external host (201; 401) through the CXL switch (SW_CXL).

Description

BACKGROUND 1. Field One or more example embodiments of the present disclosure relates to a semiconductor memory device, and more particularly, to an operation method of a host configured to communicate with storage devices and memory devices, and a system including the storage devices and the memory devices. 2. Description of Related Art A semiconductor memory device is classified as a volatile memory device, in which stored data disappear when a power is turned off, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory device, in which stored data are retained even when a power is turned off, such as a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM). A storage device such as a solid state drive may include a flash memory. A system of logical block addresses used in a host is different from a system of physical block addresses of the flash memory of the storage device. For this reason, the storage device may perform negotiation between a logical block address of the host and a physical block address of the flash memory by using map data in which the logical block address and the physical block address are mapped. As the capacity of the flash memory increases, the capacity of the map data may also increase. As such, there may be required a high-capacity buffer memory to be used in the storage device, thereby causing costs for new research and development. SUMMARY Provided are an operation method of a host configured to communicate with storage devices and memory devices capable of managing a large amount of map data without a high-capacity buffer memory dedicated for a storage device, and a system including the storage devices and the memory devices. The invention is set out in the appended claims. Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments. According to an aspect of an example embodiments, a system may include a first compute express link (CXL) storage device, a second CXL storage device, a first CXL memory device, and a CXL switch connected to the first CXL storage device, the second CXL storage device and the first CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device and the second CXL storage device, and the first CXL memory device. The first CXL memory device may be configured to store first map data of the first CXL storage device and second map data of the second CXL storage device, the first CXL storage device may be configured to exchange at least a portion of the first map data with the first CXL memory device through the CXL switch, and the second CXL storage device may be configured to exchange at least a portion of the second map data with the first CXL memory device through the CXL switch. According to an aspect of an example embodiment, a system may include a first CXL storage device, a first CXL memory device, a second CXL memory device, and a CXL switch connected to the first CXL storage device, the first CXL memory device and the second CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device, and the first CXL memory device and the second CXL memory device. At least one of the first CXL memory device and the second CXL memory device may be configured to store first map data of the first CXL storage device, and the first CXL storage device may be configured to exchange at least a portion of the first map data with the at least one of the first CXL memory device and the second CXL memory device. According to an aspect of an example embodiment, a method of a host configured to communicate with a plurality of CXL storage devices and a plurality of CXL memory devices may include identifying storage information of each of the plurality of CXL storage devices, identifying memory information of each of the plurality of CXL memory devices, and allocating, based on the storage information, a dedicated memory area for each of the plurality of CXL storage devices from at least two of the plurality of CXL memory devices. The plurality of CXL storage devices, the plurality of CXL memory devices, and the host may communicate through a CXL interface, and map data of each of the plurality of CXL storage devices may be stored in respective allocated dedicated memory areas. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of certain example embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram illustrating a computing system including a storage device according to related art;FIG. 2 is a block diagram illustrating a computing s