EP-4738138-A1 - A RECONFIGURABLE INTEGRATED CIRCUIT (IC) DEVICE AND A SYSTEM AND METHOD OF CONFIGURING THEREOF

Abstract

An Integrated Circuit (IC) device, and a method of utilizing thereof, may include: a plurality of Processing Elements (PEs), each comprising one or more configurable hardware logic blocks. The IC may further include a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE. The IC may further include a configuration manager circuit, configured to: receive a reconfiguration instruction, dictating a required function of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; based on the required function, select a specific configuration setting in the configuration memory element associated with the at least one target PE; and reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting.

Inventors

• RAZ, Elad
• TAYARI, ILAN
• GAL, RONEN
• MARGALIT, ODED
• Shliselberg, Elad

Assignees

• Next Silicon Ltd

Dates

Publication Date

20260506

Application Date

20251103

Claims (15)

1. An Integrated Circuit (IC) device comprising: a plurality of Processing Elements (PEs), each comprising one or more configurable hardware logic blocks; a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE; and a configuration manager circuit, wherein said configuration manager circuit is configured to: receive a reconfiguration instruction, dictating a required function of at least part of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; based on the required function, select a specific configuration setting in the configuration memory element associated with the at least one target PE; and reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting.
2. The IC device of claim 1, wherein the one or more hardware logic blocks comprise (i) a computational unit, and (ii) at least one set of configuration registers, and wherein the configuration manager circuit is further configured to: calculate a difference between a current configuration setting, and a previous, or default configuration setting of the two or more configuration settings; and load the calculated difference to a set of configuration registers in a specific hardware logic block of the at least one target PE, thereby reconfiguring operation of the specific hardware logic block of the at least one target PE.
3. The IC device according to any one of claims 1-2, wherein the at least one identified target PE comprises a plurality of target PEs, wherein the one or more hardware logic blocks comprise at least one set of configuration registers, and wherein the configuration manager circuit is further configured to: halt operation of the plurality of target PEs; load the selected configuration setting from the configuration memory element of the target PE to specific sets of configuration registers of respective target PEs; and restart operation of the plurality of target PEs in parallel, allowing the specific sets of configuration registers to control operation of respective target PEs, thereby reconfiguring operation of the plurality of target PEs, substantially simultaneously.
4. The IC device according to any one of claims 1-3, wherein at least one hardware logic block comprises (i) a computational unit, and (ii) at least two sets of configuration registers, and wherein the configuration manager circuit is adapted to reconfigure a target PE by: loading the selected configuration setting from the configuration memory element of the target PE to a specific set of configuration registers of the at least two sets of configuration registers; and switching the specific set of configuration registers to control operation of the computational unit of the target PE.
5. The IC device according to any one of claims 1-4, wherein the at least one identified target PE comprises a plurality of target PEs, and wherein the configuration manager circuit is adapted to configure the plurality of target PEs in parallel, substantially simultaneously.
6. The IC device of claim 5, wherein the configuration manager circuit is adapted to: based on the reconfiguration instruction, produce a plurality of read access requests, wherein each read access request: (i) designates a specific target PE as a recipient, and (ii) includes a reference to the selected configuration setting in the configuration memory element associated with the recipient target PE; receive, from each PE of the plurality of target PEs, a load-complete indication, representing finalization of loading the configuration setting onto at least one hardware logic block of that PE; and simultaneously switch the plurality of target PEs, such that each operates according to a respective loaded configuration setting, thereby providing the required function, as dictated by the reconfiguration instruction.
7. The IC device of claim 6, wherein each PE comprises at least one configuration bus, concatenating the hardware logic blocks of that PE, and wherein each hardware logic block comprises a set of configuration registers, adapted to control operation of that hardware logic block, and wherein each recipient PE is adapted to: receive, from the respective configuration memory element, a response to the read access request; based on the response, produce a configuration data stream comprising one or more entries; propagate the configuration data stream through the hardware logic blocks via the at least one configuration bus, to load the sets of configuration registers of individual hardware logic blocks; and produce the load-complete indication when the configuration data stream traverses a last hardware logic block of the concatenated hardware logic blocks.
8. The IC device of claim 7, wherein the at least one configuration bus comprises a plurality of configuration buses, each concatenating a unique portion of hardware logic blocks of the recipient PE.
9. The IC device of claim 8, wherein each entry of the configuration data stream comprises (i) an identification of one or more configuration registers in a hardware logic block of the recipient PE, and (ii) configuration data, to be loaded to the identified one or more configuration registers.
10. The method of claim 9, wherein the configuration data comprises a calculated difference between a current configuration setting of the two or more configuration settings, and a previous configuration setting of the two or more configuration settings.
11. The IC device according to any one of claims 1-10, further comprising a plurality of program data memory elements, each associated with a PE of the one or more identified PEs, wherein the two or more configuration settings correspond to respective, consecutive stages in a pipeline of a computational process, and wherein the configuration manager circuit is adapted to configure the at least one hardware logic block of the identified at least one PE during run-time, while maintaining content of the respective program data memory element, thereby transferring program data between stages of the pipeline.
12. The IC device according to any one of claims 1-11, further comprising a reconfiguration scheduler, adapted to: employ a plurality of buffer devices, each dedicated to managing execution of a specific hardware-implemented function by one or more threads of the multi-thread application; monitor congestion of the buffer devices, to identify a required change in a function of at least one hardware logic block; and produce the reconfiguration instruction, based on said identification.
13. A method of reconfiguring an IC device, the method comprising: obtaining an IC device, comprising (i) a plurality of PEs, each comprising at least two sets of configuration registers, (ii) a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain at least one configuration setting of the respective PE, and (iii) a configuration manager circuit; and adapting the configuration manager circuit to: receive a reconfiguration instruction, dictating a required function of the IC device; based on the reconfiguration instruction, identify at least one target PE of the plurality of PEs as a target for reconfiguration; load the at least one configuration setting from the configuration memory element associated with the target PE to a specific set of configuration registers of the at least two sets of configuration registers; and switch the specific set of configuration registers, to control operation of the at least one target PE.
14. The method of claim 13, wherein one or more configuration memory elements of the plurality of configuration memory elements are adapted to maintain a plurality of configuration settings of the respective PE, and wherein the method further comprises adapting the configuration manager circuit to: based on the required function, selecting a specific configuration setting of the plurality of configuration settings, in a configuration memory element associated with the at least one target PE; and loading the selected configuration setting to the specific set of configuration registers, thereby reconfiguring the at least one target PE.
15. The method according to any one of claims 13-14, wherein the at least one identified target PE comprises a plurality of target PEs, and wherein the method further comprises adapting the configuration manager circuit to: based on the reconfiguration instruction, produce a plurality of read access requests, wherein each read access request: (i) designates a specific target PE as a recipient, and (ii) includes a reference to the selected configuration setting in the configuration memory element associated with the recipient target PE; receive, from each PE of the plurality of target PEs, a load-complete indication, representing finalization of loading the configuration setting onto at least one hardware logic block of that PE; and simultaneously switch the plurality of target PEs, such that each target PE operates according to a respective loaded configuration setting, thereby providing the required function, as dictated by the reconfiguration instruction.

Description

FIELD OF THE INVENTION The present invention relates generally to electronic circuit devices. More specifically, the present invention relates to Integrated Circuit (IC) devices, and methods and mechanisms of configuring thereof. BACKGROUND OF THE INVENTION Reconfigurable hardware, such as Field-Programmable Gate Arrays (FPGAs) and Coarse-Grained Reconfigurable Arrays (CGRAs), has become increasingly popular due to its flexibility and adaptability in executing a variety of computational tasks. These devices can be tailored to specific applications through reconfiguration, offering performance and energy efficiency advantages over traditional, fixed-function hardware, which are optimized to a wide range of applications (general purpose). However, one significant shortcoming of currently available reconfigurable hardware technology is the long reconfiguration period, which limits their effectiveness in handling real-time changes in the type of tasks. CGRAs, despite their flexibility in handling diverse high-level applications, often suffer from lengthy reconfiguration processes. The time required to adjust the configuration of the processing elements and the interconnect fabric can be substantial, impacting the ability of CGRAs to quickly adapt to changing workloads. This latency in reconfiguration reduces their suitability for real-time and dynamic applications, where rapid responsiveness is crucial. Similarly, FPGAs, known for their fine-grained reconfigurability and precise control over computational tasks, also face challenges with reconfiguration times. Programming an FPGA to switch between different tasks or optimize for varying conditions is a lengthy process, hindering the deployment of FPGAs in applications where quick adaptability is essential. There is therefore a need for advancements in reconfigurable hardware technologies that can significantly reduce reconfiguration times, thereby enhancing their practicality and integration into modern, real-time, adapting High Performance Computing (HPC) environments. SUMMARY OF THE INVENTION Embodiments of the invention may include an Integrated Circuit (IC) device. The IC device may include a plurality of Processing Elements (PEs), where one or more (e.g., each) PE may include one or more configurable hardware logic blocks. Additionally, the reconfigurable IC device may include a plurality of configuration memory elements, each associated with a respective PE, and adapted to maintain two or more configuration settings of the respective PE. In some embodiments, each configuration memory element may be uniquely associated (e.g., included in, or physically adjacent) the respective PE. Additionally, or alternatively, one or more configuration memory elements may be associated with a group, or subset of respective PEs. Additionally, or alternatively, the reconfigurable IC device may include a configuration manager circuit, adapted to receive a reconfiguration instruction, dictating a required function of at least a portion of (e.g., one or more PEs of) the IC device. Based on the reconfiguration instruction, the configuration manager circuit may identify at least one target PE of the plurality of PEs as a target for reconfiguration. Additionally, based on the reconfiguration instruction (e.g., on the required function), the configuration manager circuit may select a specific configuration setting in the configuration memory element associated with the at least one target PE. As elaborated herein, the configuration manager circuit may subsequently communicate with, or control the target PE to reconfigure at least one hardware logic block of the at least one target PE, according to the selected configuration setting, thereby reconfiguring the operation of the IC. According to some embodiments, the one or more hardware logic blocks may include (i) a computational unit, and (ii) at least one set of configuration registers. The configuration manager circuit may be further configured to calculate a difference between a current configuration setting, and a previous, or default configuration setting of the two or more configuration settings. The configuration manager circuit may then load the calculated difference to a set of configuration registers in a specific hardware logic block of the at least one target PE. The configuration manager circuit may thereby reconfigure operation of the specific hardware logic block of the at least one target PE. Additionally, or alternatively, the at least one identified target PE may include a plurality of target PEs, and the one or more hardware logic blocks comprise at least one set of configuration registers. The configuration manager circuit may further be configured to (a) halt operation of the plurality of target PEs, (b) load the selected configuration setting from the configuration memory element of the target PE to specific sets of configuration registers of respective target PEs, and (c) restart, or resume operation of the