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EP-4738165-A2 - BOOT CODE PATCHING APPARATUS AND METHOD, MEDIUM, DEVICE, AND SYSTEM ON CHIP

EP4738165A2EP 4738165 A2EP4738165 A2EP 4738165A2EP-4738165-A2

Abstract

Embodiments of the present disclosure disclose a boot code patching apparatus and method, a medium, a device, and a system on chip. A first memory stores a boot code, and a second memory stores preset patch data. The processor reads the boot code from the first memory and executes the boot code; reads the patch data from the second memory in response to the execution proceeding to a first preset instruction; sets a breakpoint for the boot code through a debug control channel based on the patch data, and continues executing the boot code; in response to the execution proceeding to any breakpoint of the boot code, jumps to a patch code corresponding to that breakpoint in the patch data; and in response to execution of the patch code corresponding to the breakpoint being completed, jumps to a return address corresponding to the breakpoint, and continues executing the boot code.

Inventors

  • LIN, TAO
  • ZHANG, WENBIN

Assignees

  • XG TECH PTE. LTD.

Dates

Publication Date
20260506
Application Date
20260319

Claims (15)

  1. A boot code patching apparatus, characterized in that the boot code patching apparatus comprises: a first memory (22), configured to store a boot code; a second memory (23), configured to store preset patch data; and a processor (21), configured to: read the boot code from the first memory (22) and execute the boot code; read the patch data from the second memory (23) in response to a first preset instruction in the boot code; set a breakpoint for the boot code through a debug control channel (30), based on the patch data; in response to the execution proceeding to the breakpoint of the boot code, jump to a patch code corresponding to the breakpoint in the patch data; and in response to execution of the patch code corresponding to the breakpoint being completed, jump to a return address corresponding to the breakpoint, and continue executing the boot code.
  2. The apparatus according to claim 1, wherein after reading the patch data from the second memory (23), the processor (21) is specifically configured to: configure and open a debug control channel (30); determine, based on the patch data, patch information corresponding to at least one patch, wherein the patch information corresponding to any patch comprises a source address corresponding to that patch; and set at least one breakpoint for the boot code based on the source address corresponding to the at least one patch, and configure a debug logic unit (31), so that the debug logic unit (31) can generate debug exception information corresponding to the breakpoint when the execution proceeds to the breakpoint.
  3. The apparatus according to claim 2, wherein the configuring and opening a debug control channel (30) comprises: configuring a first preset register corresponding to the debug control channel (30) to a first preset status; and/or, the configuring a debug logic unit (31) comprises: configuring a second preset register corresponding to the debug logic unit (31) to a second preset status.
  4. The apparatus according to claim 1, wherein the in response to the execution proceeding to the breakpoint of the boot code, jumping to a patch code corresponding to the breakpoint in the patch data comprises: in response to the execution proceeding to the breakpoint of the boot code, generating target debug exception information corresponding to the breakpoint by the debug logic unit (31); determining, based on the target debug exception information, a patch code of a target patch corresponding to the breakpoint from the patch data, and determining the patch code of the target patch as the patch code corresponding to the breakpoint; and executing the patch code corresponding to the breakpoint.
  5. The apparatus according to claim 4, wherein after reading the patch data from the second memory (23), the processor (21) is further configured to: store the patch data into a third memory (24), which is a volatile memory; and the determining, based on the target debug exception information, a patch code of a target patch corresponding to the breakpoint from the patch data comprises: determining, based on the target debug exception information, a target source address corresponding to the breakpoint; reading the patch data from the third memory (24), and determining, based on the patch data, patch information corresponding to at least one patch, wherein the patch information corresponding to any patch comprises a source address, a return address, and a patch code corresponding to that patch; and matching the target source address with the source address in the patch information corresponding to the at least one patch, and determining, based on a matching result, the patch code of the target patch corresponding to the breakpoint.
  6. The apparatus according to claim 4, wherein after reading the patch data from the second memory (23), the processor (21) is further configured to: parse the patch data according to a preset patch format to obtain patch information corresponding to at least one patch, wherein the patch information corresponding to any patch comprises a source address, a return address, and a patch code corresponding to that patch; and store the patch information corresponding to the at least one patch into a third memory (24), which is a volatile memory; and the determining, based on the target debug exception information, a patch code of a target patch corresponding to the breakpoint from the patch data comprises: determining, based on the target debug exception information, a target source address corresponding to the breakpoint; reading the patch information corresponding to the at least one patch from the third memory (24); and matching the target source address with the source address in the patch information corresponding to the at least one patch, and determining, based on a matching result, the patch code of the target patch corresponding to the breakpoint.
  7. The apparatus according to claim 4, wherein the patch data comprises a return address corresponding to at least one patch; and the in response to execution of the patch code corresponding to the breakpoint being completed, jumping to a return address corresponding to the breakpoint, and continuing executing the boot code comprises: in response to the execution of the patch code corresponding to the breakpoint being completed, obtaining the return address corresponding to the breakpoint from the patch data; and jumping to the return address, and executing an instruction corresponding to the return address in the boot code.
  8. The apparatus according to any one of claims 1 to 7, wherein the second memory (23) is a one-time programmable memory; and after reading the patch data from the second memory (23), the processor (21) is further configured to: perform legitimacy and integrity verification on the patch data, to obtain a verification result; and the setting a breakpoint for the boot code through a debug control channel (30) based on the patch data comprises: in response to the verification result being passed, setting a breakpoint for the boot code through the debug control channel (30) based on the patch data.
  9. A boot code patching method, characterized in that the boot code patching method comprises: reading (510) a boot code from a first memory and executing the boot code; reading (520) patch data from a second memory in response to a first preset instruction in the boot code; setting (530) a breakpoint for the boot code through a debug control channel based on the patch data; in response to the execution proceeding to the breakpoint of the boot code, jumping (540) to a patch code corresponding to the breakpoint in the patch data; and in response to execution of the patch code corresponding to the breakpoint being completed, jumping (550) to a return address corresponding to the breakpoint, and continuing executing the boot code.
  10. A computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is executed by a processor to implement the boot code patching method according to claim 9.
  11. An electronic device (90), characterized in that the electronic device comprises: a processor (91); and a memory (92), configured to store processor-executable instructions, wherein the processor (91) is configured to read the executable instructions from the memory (92), and execute the executable instructions to implement the boot code patching method according to claim 9.
  12. A system on chip, characterized in that the system on chip comprises: a boot code patching apparatus, wherein the boot code patching apparatus comprises: a first memory (22), configured to store a boot code; a second memory (23), configured to store preset patch data; and a processor (21), configured to: read the boot code from the first memory (22) and execute the boot code; read the patch data from the second memory (23) in response to a first preset instruction in the boot code; set a breakpoint for the boot code through a debug control channel (30), based on the patch data; in response to the execution proceeding to the breakpoint of the boot code, jump to a patch code corresponding to the breakpoint in the patch data; and in response to execution of the patch code corresponding to the breakpoint being completed, jump to a return address corresponding to the breakpoint, and continue executing the boot code.
  13. The system on chip according to claim 12, wherein after reading the patch data from the second memory (23), the processor (21) is specifically configured to: configure and open a debug control channel (30); determine, based on the patch data, patch information corresponding to at least one patch, wherein the patch information corresponding to any patch comprises a source address corresponding to that patch; and set at least one breakpoint for the boot code based on the source address corresponding to the at least one patch, and configure a debug logic unit (31), so that the debug logic unit (31) can generate debug exception information corresponding to the breakpoint when the execution proceeds to the breakpoint.
  14. The system on chip according to claim 13, wherein the configuring and opening a debug control channel (30) comprises: configuring a first preset register corresponding to the debug control channel (30) to a first preset status; and/or, the configuring a debug logic unit (31) comprises: configuring a second preset register corresponding to the debug logic unit (31) to a second preset status.
  15. The system on chip according to claim 12, wherein the in response to the execution proceeding to the breakpoint of the boot code, jumping to a patch code corresponding to the breakpoint in the patch data comprises: in response to the execution proceeding to the breakpoint of the boot code, generating target debug exception information corresponding to the breakpoint by the debug logic unit (31); determining, based on the target debug exception information, a patch code of a target patch corresponding to the breakpoint from the patch data, and determining the patch code of the target patch as the patch code corresponding to the breakpoint; and executing the patch code corresponding to the breakpoint.

Description

FIELD OF THE INVENTION The present disclosure relates to technologies of integrated circuits, and in particular, to a boot code patching apparatus and method, a medium, a device, and a system on chip. BACKGROUND OF THE INVENTION An electronic device (or a system on chip) typically executes a boot code (or referred to as a bootstrap code) when powered on, to initialize a resource or a component of the electronic device, and load and run an operating system. To avoid execution of unauthorized software on the electronic device, the boot code may verify legitimacy of the operating system and application software through a secure boot mechanism. Being a lowest-level code executed during startup of the electronic device, the boot code is generally hardcoded into a read-only memory (ROM) of the electronic device to avoid malicious modification of the boot code. The hardened boot code may be referred to as a ROM code. If an error occurs in the ROM code, the ROM code also cannot be modified to correct the error. To correct the error in the ROM code, in related technologies, an instruction in the ROM code is usually modified by adding hardware logic. The hardware logic includes, for example, a storage unit, a comparison unit, a branch instruction generator, and a multiplexer. The added hardware logic makes hardware implementation of the electronic device more complex. SUMMARY OF THE INVENTION Embodiments of the present disclosure provide a boot code patching apparatus and method, a medium, a device, and a system on chip, to implement effective patching of a boot code without increasing complexity of hardware implementation. According to a first aspect of an embodiment of the present disclosure, a boot code patching apparatus is provided, including: a first memory, configured to store a boot code; a second memory, configured to store preset patch data; and a processor, configured to: read the boot code from the first memory and execute the boot code; read the patch data from the second memory in response to a first preset instruction in the boot code; set a breakpoint for the boot code through a debug control channel based on the patch data; in response to the execution proceeding to the breakpoint of the boot code, jump to a patch code corresponding to the breakpoint in the patch data; and in response to execution of the patch code corresponding to the breakpoint being completed, jump to a return address corresponding to the breakpoint, and continue executing the boot code. According to a second aspect of an embodiment of the present disclosure, a boot code patching method is provided, including: reading a boot code from a first memory and executing the boot code; reading patch data from a second memory in response to a first preset instruction in the boot code; setting a breakpoint for the boot code through a debug control channel based on the patch data; in response to the execution proceeding to the breakpoint of the boot code, jumping to a patch code corresponding to the breakpoint in the patch data; and in response to execution of the patch code corresponding to the breakpoint being completed, jumping to a return address corresponding to the breakpoint, and continuing executing the boot code. According to a third aspect of an embodiment of the present disclosure, a computer readable storage medium is provided. The storage medium stores a computer program, and the computer program is executed by a processor to implement the boot code patching method according to any one of the foregoing embodiments of the present disclosure. According to a fourth aspect of an embodiment of the present disclosure, an electronic device is provided. The electronic device includes: a processor; and a memory, configured to store processor-executable instructions. The processor is configured to read the executable instructions from the memory, and execute the executable instructions to implement the boot code patching method according to any one of the foregoing embodiments of the present disclosure. According to a fifth aspect of an embodiment of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the boot code patching method according to any one of the foregoing embodiments of the present disclosure is implemented. According to the boot code patching apparatus and method, the medium, the device, and the system on chip that are provided in the foregoing embodiments of the present disclosure, the boot code is stored by the first memory, and the preset patch data is stored by the second memory. During startup of the electronic device or the system on chip, the processor may read the boot code from the first memory and execute the read boot code; read the patch data from the second memory in response to the execution proceeding to the first preset instruction in the boot code; further set the breakpoint for the boot code through the debug control