EP-4738180-A1 - CHIP POWER CONSUMPTION EVALUATION METHOD, POWER CONSUMPTION MODEL GENERATION METHOD, AND COMPUTER DEVICE

EP4738180A1EP 4738180 A1EP4738180 A1EP 4738180A1EP-4738180-A1

Abstract

The present application relates to a chip power consumption evaluation method, a power consumption model generation method, and a computer device. The chip power consumption evaluation method comprises : determining a static modeling parameter and a dynamic evaluation parameter of a chip under test, wherein the static modeling parameter describes a constant chip design parameter in a power consumption constraint condition of a current power consumption scenario, and the dynamic evaluation parameter is a varying chip design parameter in the power consumption constraint condition of the current power consumption scenario; performing calculation on the basis of the static modeling parameter and a first mapping relationship to obtain an intermediate calculation result, and generating a target power consumption model which stores the intermediate calculation result, wherein the first mapping relationship is at least used for indicating the correspondence between the static modeling parameter and the intermediate calculation result; and obtaining a power consumption evaluation result on the basis of the dynamic evaluation parameter and the target power consumption model. By means of the present application, the problem of low efficiency of the chip power consumption evaluation method is solved, and an efficient and accurate chip power consumption evaluation method is achieved.

Inventors

Zhang, Runjie

Assignees

Phlexing Technology Co.,Ltd

Dates

Publication Date: 20260506
Application Date: 20240529

Claims (13)

A chip power consumption evaluation method, comprising: determining a static modeling parameter and a dynamic evaluation parameter of a chip under tested; wherein the static modeling parameter is an unvarying chip design parameter in a power consumption constraint of a current power consumption scenario, and the dynamic evaluation parameter is a varying chip design parameter in the power consumption constraint of the current power consumption scenario; calculating an intermediate calculation result based on the static modeling parameter and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation result; wherein the first mapping relationship is used to indicate a correspondence between the static modeling parameter in the power consumption constraint and the intermediate calculation result; obtaining a power consumption evaluation result based on the dynamic evaluation parameter and the target power consumption model.
The chip power consumption evaluation method according to claim 1, wherein: determining the static modeling parameter of the chip under tested comprises: obtaining a static factor information corresponding to a scenario requirement information, and determining the static modeling parameter of the chip under tested from the static factor information; and/or, determining the dynamic evaluation parameter of the chip under tested comprises: obtaining a dynamic factor information corresponding to the scenario requirement information, and determining the dynamic evaluation parameter of the chip under tested from the dynamic factor information.
The chip power consumption evaluation method according to claim 1, wherein generating the target power consumption model that stores the intermediate calculation result comprises: determining a data template corresponding to the scenario requirement information; obtaining a model data required by the data template from the intermediate calculation result; generating the target power consumption model based on the model data and the data template.
The chip power consumption evaluation method according to claim 1, wherein the target power consumption model comprises a detailed model data; wherein the detailed model data at least comprises a chip description data and the intermediate calculation result corresponding to the chip description data; and/or, the target power consumption model comprises a model metadata; wherein the model metadata at least comprises a model description data, and the model description data is used to describe an attribute of the target power consumption model.
The chip power consumption evaluation method according to claim 1, wherein obtaining the power consumption evaluation result based on the dynamic evaluation parameter and the target power consumption model comprises: determining a second mapping relationship; wherein the second mapping relationship is used to indicate a correspondence between the dynamic evaluation parameter in the power consumption constraint, the intermediate calculation result of the target power consumption model, and the power consumption evaluation result; obtaining the power consumption evaluation result based on the dynamic evaluation parameter, the intermediate calculation result, and the second mapping relationship.
The chip power consumption evaluation method according to claim 1, wherein the static modeling parameter comprises at least one hierarchical sub-module of the chip under tested, and the intermediate calculation result of the target power consumption model comprise an intermediate calculation result corresponding to the hierarchical sub-module.
The chip power consumption evaluation method according to claim 6, wherein each hierarchical sub-module comprises multiple component units, and calculating the intermediate calculation result based on the static modeling parameter and the first mapping relationship comprises: for each component unit, obtaining a static modeling parameter corresponding to different power consumption types of the component unit, and first mapping relationships corresponding to different power consumption types; wherein a same power consumption type corresponds to a same first mapping relationship; calculating intermediate calculation results for different power consumption evaluation types of different component units, based on the static modeling parameter corresponding to different power consumption types, and the first mapping relationship corresponding to different power consumption types; merging intermediate calculation results of the same power consumption type in a same hierarchy to generate the intermediate calculation result corresponding to the hierarchical sub-module.
The chip power consumption evaluation method according to any one of claims 1 to 7, further comprising: obtaining a block information for the chip under tested, determining at least two block chip areas of the chip under tested based on the block information; calculating the intermediate calculation result based on the static modeling parameter and the first mapping relationship, and generating the target power consumption model that stores the intermediate calculation result, comprising: generating at least two target power consumption models corresponding to the block chip areas based on the static modeling parameter, wherein each target power consumption model is used with the dynamic evaluation parameter of a corresponding block chip area, to obtain power consumption evaluation result corresponding to the block chip areas.
A chip power consumption evaluation method, comprising: in response to a user's power consumption evaluation request, obtaining a target power consumption model; wherein the target power consumption model is used to store an intermediate calculation result calculated based on a static modeling parameter of a chip under tested and a first mapping relationship, wherein the static modeling parameter is an unvarying chip design parameter in a power consumption constraint of a current power consumption scenario, and the first mapping relationship is used to indicate a correspondence between the static modeling parameter in the power consumption constraint and the intermediate calculation result; obtaining a dynamic evaluation parameter; wherein the dynamic evaluation parameter is a varying chip design parameter in the power consumption constraint of the current power consumption scenario; obtaining a power consumption evaluation result based on the dynamic evaluation parameter and the target power consumption model.
The chip power consumption evaluation method according to claim 9, wherein obtaining the power consumption evaluation result based on the dynamic evaluation parameter and the target power consumption model comprises: determining a second mapping relationship; wherein the second mapping relationship is used to indicate a correspondence between the dynamic evaluation parameter in the power consumption constraint, the intermediate calculation result of the target power consumption model, and the power consumption evaluation result; obtaining the power consumption evaluation result based on the dynamic evaluation parameter, the intermediate calculation result, and the second mapping relationship.
A power consumption model generation method, comprising: determining a static modeling parameter of a chip under tested; wherein the static modeling parameter is an unvarying chip design parameter in a power consumption constraint of a current power consumption scenario; calculating intermediate calculation result based on the static modeling parameter and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation result, to obtain a power consumption evaluation result of the chip under tested; wherein the first mapping relationship is used to indicate a correspondence between the static modeling parameter in the power consumption constraint and the intermediate calculation result; the power consumption evaluation result are generated based on a dynamic evaluation parameter and the target power consumption model, and the dynamic evaluation parameter is a varying chip design parameter in the power consumption constraint of the current power consumption scenario.
The power consumption model generation method according to claim 11, wherein the target power consumption model comprises a detailed model data; wherein the detailed model data at least comprises a chip description data and the intermediate calculation result corresponding to the chip description data; and/or, the target power consumption model comprises a model metadata; wherein the model metadata at least comprises a model description data, and the model description data is used to describe an attributes of the target power consumption model.
A computer device, comprising a memory and a processor, the memory storing a computer program, wherein when the processor executes the computer program, it implements the chip power consumption evaluation method according to any one of claims 1 to 10, or the power consumption model generation method according to any one of claims 11 or 12.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. CN202310773235.3, filed on June 28, 2023, titled "Chip Power Consumption Evaluation Method, Power Consumption Model Generation Method, and Computer Device," the entire content of which is incorporated herein by reference. TECHNICAL FIELD The present application relates to the field of chip technology, and more particularly to a chip power consumption evaluation method, a power consumption model generation method, and a computer device. BACKGROUND With the advancement of manufacturing and packaging technologies, the integration level (i.e., the number of transistors per unit volume) and power density of integrated circuits are constantly increasing, making power consumption one of the important considerations in integrated circuit design. In the related technology, power consumption evaluation techniques are usually used to evaluate integrated circuit chips at the Register Transfer Language (RTL) stage, before physical implementation, and after physical implementation. The common point of these three stages of power consumption evaluation is that all the chip elements related to power consumption evaluation need to be input at once for the overall power consumption calculation of the design. For chips of a certain scale, the amount of input data related to power consumption calculation is very large, resulting in very low efficiency in evaluating the power consumption of integrated circuit chips. At present, there is no effective solution to the problem of low efficiency in chip power consumption detection in the related technology. SUMMARY OF THE DISCLOSURE The present application provides a chip power consumption evaluation method, a power consumption model generation method, and a computer device to at least solve the problem of low efficiency in chip power consumption detection in the related technology. In a first aspect, the present application provides a chip power consumption evaluation method, which includes: determining a static modeling parameter and a dynamic evaluation parameter of a chip under tested; wherein the static modeling parameter is an unvarying chip design parameter in a power consumption constraint of a current power consumption scenario, and the dynamic evaluation parameter is a varying chip design parameter in the power consumption constraint of the current power consumption scenario;calculating an intermediate calculation result based on the static modeling parameter and a first mapping relationship, and generating a target power consumption model that stores the intermediate calculation result; wherein the first mapping relationship is used to indicate a correspondence between the static modeling parameter in the power consumption constraint and the intermediate calculation result;obtaining a power consumption evaluation result based on the dynamic evaluation parameter and the target power consumption model. In some embodiments, determining the static modeling parameter of the chip under tested includes: obtaining a static factor information corresponding to a scenario requirement information, and determining the static modeling parameter of the chip under tested from the static factor information; and/or, determining the dynamic evaluation parameter of the chip under tested includes: obtaining a dynamic factor information corresponding to the scenario requirement information, and determining the dynamic evaluation parameter of the chip under tested from the dynamic factor information. In some embodiments, generating the target power consumption model that stores the intermediate calculation result includes: determining a data template corresponding to the scenario requirement information;obtaining a model data required by the data template from the intermediate calculation results;generating the target power consumption model based on the model data and the data template. In some embodiments, the target power consumption model includes detailed model data; wherein the detailed model data at least includes a chip description data and the intermediate calculation result corresponding to the chip description data; and/or, the target power consumption model includes a model metadata; wherein the model metadata at least includes model description data, and the model description data is used to describe an attributes of the target power consumption model. In some embodiments, the static modeling parameter includes at least one hierarchical sub-module of the chip under tested, and the intermediate calculation result includes an intermediate calculation result corresponding to the hierarchical sub-module. In some embodiments, each hierarchical sub-module includes multiple component units, and the method further includes: for each component unit, obtaining the static modeling parameter corresponding to different power consumption types of the component unit, and the first mapping re