EP-4738198-A2 - ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK WITH SUBSTANTIALLY CONSTANT ARRAY SOURCE IMPEDANCE WITH ADAPTIVE WEIGHT MAPPING AND DISTRIBUTED POWER

EP4738198A2EP 4738198 A2EP4738198 A2EP 4738198A2EP-4738198-A2

Abstract

Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Inventors

TRAN, HIEU VAN
VU, THUAN
TRINH, STEPHEN
HONG, STANLEY
LY, ANH
TIWARI, Vipin

Assignees

Silicon Storage Technology Inc.

Dates

Publication Date: 20260506
Application Date: 20200903

Claims (3)

A method of operating an analog neural memory system comprising an array of non-volatile memory cells, the method comprising: receiving, by a first n-bit analog-to-digital converter, a first output from the array; receiving, by a second n-bit analog-to-digital converter, a second output from the array; combining the first n-bit analog-to-digital converter with the second n-bit analog-to-digital converter to form a third analog-to-digital converter that generates a third output based on the first output and the second output, wherein the third output has a precision greater than n bits.
The method of claim 1, wherein the first analog-to-digital converter is a serial analog-to-digital converter and the second analog-to-digital converter is a serial analog-to-digital converter.
The method of claim 1, wherein the first analog-to-digital converter is a successive approximation converter and the second analog-to-digital converter is a successive approximation converter.

Description

PRIORITY CLAIMS This application claims priority to U.S. Provisional Application No. 62/985,826, filed on March 5, 2020, and titled, "Analog Neural Memory Array in Artificial Neural Network With Accurate Array Source Impedance With Adaptive Weight Mapping and Distributed Power," and, U.S. Patent Application No. 16/986,812, filed on August 6, 2020, and titled, "Analog Neural Memory Array in Artificial Neural Network with Substantially Constant Array Source Impedance with Adaptive Weight Mapping and Distributed Power." FIELD OF THE INVENTION Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise. BACKGROUND OF THE INVENTION Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected "neurons" which exchange messages between each other. Figure 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows, and have numeric weights that can be tuned based on experience. This makes the artificial neural network adaptive to inputs and capable of learning. Typically, artificial neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses. One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical artificial neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e. a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or specialized graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses. Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application No. 15/594,439, published as US Patent Publication 2017/0337466, which is incorporated by reference. The non-volatile memory arrays operate as an analog neuromorphic memory. The term neuromorphic, as used herein, means circuitry that implement models of neural systems. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. An array of memory cells arranged in this manner can be referred to as a vector by matrix multiplication (VMM) array. Examples of different non-volatile memory cells that can be used in VMMs will now be discussed. Non-Volatile Memory Cells Various types of known non-volatile memory cells can be used in the VMM arrays. For example, U.S. Patent 5,029,130 ("the '130 patent"), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel r