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EP-4738328-A1 - GATE DRIVER AND ELECTRONIC DEVICE HAVING THE SAME

EP4738328A1EP 4738328 A1EP4738328 A1EP 4738328A1EP-4738328-A1

Abstract

A gate driver includes an input circuit to transmit an input signal to a first control node responsive to a first clock signal; a pull-up circuit to pull up a gate output signal to a high voltage responsive to a signal of a second control node; a pull-down circuit to pull down the gate output signal to a first low voltage responsive to a signal of a third control node; a node separating circuit including a control electrode to receive the high voltage, a first electrode connected to the first control node and a second electrode connected to the second control node; a first control node control circuit to control a signal of the first control node responsive to the signal of the third control node; and a third control node control circuit to control the signal of the third control node responsive to the signal of the first control node.

Inventors

  • JEONG, JUNKI
  • SEO, YOUNGWAN
  • AN, Jongyeop

Assignees

  • Samsung Display Co., Ltd.

Dates

Publication Date
20260506
Application Date
20251023

Claims (15)

  1. A gate driver (300, 300a, 300b, 300c) comprising a plurality of stages, wherein a stage of the plurality of stages comprises: a first transistor comprising a first sub-transistor including a control electrode connected to a first clock signal line, a first electrode connected to an input signal line and a second electrode connected to a first intermediate node, and a second sub-transistor including a control electrode connected to the first clock signal line, a first electrode connected to the first intermediate node (NA) and a second electrode connected to a first control node (Q); a second transistor comprising a first sub-transistor including a control electrode connected to a third control node (QB), a first electrode connected to the first intermediate node (NA) and a second electrode connected to the first control node (Q), and a second sub-transistor including a control electrode connected to the third control node (QB), a first electrode connected to a second low voltage line and a second electrode connected to the first intermediate node (NA); a third transistor (T3) including a control electrode connected to a high voltage line, a first electrode connected to the first control node (Q) and a second electrode connected to a second control node (QF); a fifth transistor (T5) including a control electrode connected to the second control node (QF), a first electrode connected to the high voltage line and a second electrode connected to a carry output terminal; a sixth transistor (T6) including a control electrode connected to the third control node (QB), a first electrode connected to the second low voltage line and a second electrode connected to the carry output terminal; a seventh transistor (T7) including a control electrode connected to the second control node (QF), a first electrode connected to the high voltage line and a second electrode connected to a gate output terminal (OT[1] - OT[5]); and an eighth transistor (T8) including a control electrode connected to the third control node (QB), a first electrode connected to a first low voltage line and a second electrode connected to the gate output terminal (OT[1] - OT[5]).
  2. The gate driver (300, 300a, 300b, 300c) of claim 1, wherein the stage of the plurality of stages further comprises: a fourth transistor (T4) including a control electrode connected to the second control node (QF), a first electrode connected to a second clock signal line and a second electrode connected to a second electrode of a first capacitor (C1), wherein the first capacitor (C1) includes a first electrode connected to the second control node (QF).
  3. The gate driver (300, 300a, 300b, 300c) of claim 1 or 2, wherein the stage of the plurality of stages further comprises a second capacitor (C2) including a first electrode connected to the second control node (QF) and a second electrode connected to the gate output terminal (OT[1] - OT[5]).
  4. The gate driver (300, 300a, 300b, 300c) of claims 1 to 3, wherein the stage (310a, 310c) of the plurality of stages (310a, 310c) further comprises: a ninth transistor comprising a first sub-transistor including a control electrode connected to the high voltage line, a first electrode connected to a first node (NB) and a second electrode connected to a ninth intermediate node, and a second sub-transistor including a control electrode to the high voltage line, a first electrode connected to the ninth intermediate node and a second electrode connected to the high voltage line; and a tenth transistor (T10) including a control electrode connected to the first node (NB), a first electrode connected to the high voltage line and a second electrode connected to the third control node (QB) and/or wherein the stage of the plurality of stages further comprises a third capacitor including a first electrode connected to the first node (NB) and a second electrode connected to the third control node (QB) and/or wherein the stage of the plurality of stages further comprises: an eleventh transistor (T11) including a control electrode connected to the first control node (Q), a first electrode connected to the first low voltage line and a second electrode connected to the first node (NB); and a twelfth transistor (T12) including a control electrode connected to the first control node (Q), a first electrode connected to the second low voltage line and a second electrode connected to the third control node (QB).
  5. The gate driver (300, 300a, 300b, 300c) of claims 1 to 4, wherein the stage of the plurality of stages further comprises: a thirteenth transistor comprising a first sub-transistor including a control electrode connected to the first control node (Q), a first electrode connected to the high voltage line and a second electrode connected to a thirteenth intermediate node, and a second sub-transistor including a control electrode connected to the first control node (Q), a first electrode connected to the thirteenth intermediate node and a second electrode connected to the first intermediate node.
  6. The gate driver (300, 300a, 300b, 300c) of claims 1 to 5, wherein the stage of the plurality of stages further comprises: a fourteenth transistor comprising a first sub-transistor including a control electrode connected to a reset signal line, a first electrode connected to the first intermediate node (NA) and a second electrode connected to the first control node (Q), and a second sub-transistor including a control electrode connected to the reset signal line, a first electrode connected to the first low voltage line and a second electrode connected to the first intermediate node.
  7. The gate driver (300, 300a, 300b, 300c) of claims 1 to 6, wherein: the plurality of stages (310a, 310c) comprises a first stage (ST[1]), a second stage (ST[2]), a third stage (ST[3]) and a fourth stage (ST[4]) which are sequentially disposed, a carry signal of the first stage (ST[1]) is connected to the second stage (ST[2]), a carry signal of the second stage (ST[2]) is connected to the third stage (ST[3]), a carry signal of the third stage (ST[3]) is connected to the fourth stage (ST[4]), the first clock signal line is connected to a first clock terminal of the first stage (ST[1]) and a second clock signal line is connected to a second clock terminal of the first stage (ST[1]), the second clock signal line is connected to a first clock terminal of the second stage (ST[2]) and the first clock signal line is connected to a second clock terminal of the second stage (ST[2]), the first clock signal line is connected to a first clock terminal of the third stage (ST[3]) and the second clock signal line is connected to a second clock terminal of the third stage (ST[3]), and the second clock signal line is connected to a first clock terminal of the fourth stage (ST[4]) and the first clock signal line is connected to a second clock terminal of the fourth stage (ST[4]).
  8. The gate driver (300, 300a, 300b, 300c) of claim 7, wherein: a cycle of a first clock signal (CLK1) of the first clock signal line is two horizontal periods, a cycle of a second clock signal (CLK2) of the second clock line signal is two horizontal periods, and a high period of a pulse of a gate output signal (OUT[n]) is two horizontal periods and/or wherein a high period of the first clock signal (CLK1) does not overlap a high period of the second clock signal.
  9. The gate driver (300, 300a, 300b, 300c) of claims 1 to 8, wherein: the plurality of stages comprises a first stage (ST[1]), a second stage (ST[2]), a third stage (ST[3]) and a fourth stage (ST[4]) which are sequentially disposed, a carry signal of the first stage (ST[1]) is connected to the third stage, a carry signal of the second stage (ST[2]) is connected to the fourth stage, the first clock signal (CLK1) is applied to a first clock terminal of the first stage (ST[1]) and a second clock signal (CLK2) is applied to a second clock terminal of the first stage, a third clock signal (CLK3) is applied to a first clock terminal of the second stage (ST[2]) and a fourth clock signal (CLK4) is applied to a second clock terminal of the second stage, the second clock signal (CLK2) is applied to a first clock terminal of the third stage (ST[3]) and the first clock signal (CLK1) is applied to a second clock terminal of the third stage, and the fourth clock signal (CLK4) is applied to a first clock terminal of the fourth stage (ST[4]) and the third clock signal (CLK3) is applied to a second clock terminal of the fourth stage.
  10. The gate driver (300, 300a, 300b, 300c) of claim 9, wherein: a cycle of the first clock signal (CLK1) is four horizontal periods, a cycle of the second clock signal (CLK2) is four horizontal periods, a cycle of the third clock signal (CLK3) is four horizontal periods, a cycle of the fourth clock signal (CLK4) is four horizontal periods, and a high period of a pulse of a gate output signal (OUT[n]) is four horizontal periods.
  11. The gate driver (300, 300a, 300b, 300c) of claim 10, wherein: a high period of the first clock signal (CLK1) does not overlap a high period of the second clock signal (CLK2), a high period of the third clock signal (CLK3) overlaps the high period of the first clock signal (CLK1), and the high period of the third clock signal (CLK3) overlaps the high period of the second clock signal (CLK2).
  12. A gate driver (300, 300a, 300b, 300c) comprising: an input circuit configured to transmit an input signal to a first control node (Q) in response to a first clock signal (CLK1); a pull-up circuit configured to pull up a gate output signal (OUT[n]) to a high voltage (VGH) in response to a signal of a second control node (QF); a pull-down circuit configured to pull down the gate output signal (OUT[n]) to a first low voltage (VGL) in response to a signal of a third control node (QB); a node separating circuit including a control electrode configured to receive the high voltage (VGH), a first electrode connected to the first control node (Q) and a second electrode connected to the second control node (QF); a first control node (Q) control circuit configured to control a signal of the first control node (Q) in response to the signal of the third control node (QB); and a third control node (QB) control circuit configured to control the signal of the third control node (QB) in response to the signal of the first control node (Q).
  13. An electronic device (101, 102, 1000, 1000a, 1000b) comprising: a display panel (100, 141) comprising a pixel; a gate driver (300, 300a, 300b, 300c) configured to output a gate signal to the pixel; and a data driver (143, 500) configured to output a data voltage to the pixel, wherein the gate driver (300, 300a, 300b, 300c) comprises: a first transistor comprising a first sub-transistor including a control electrode configured to receive a first clock signal (CLK1), a first electrode configured to receive an input signal and a second electrode connected to a first intermediate node, and a second sub-transistor including a control electrode configured to receive the first clock signal (CLK1), a first electrode connected to the first intermediate node (NA) and a second electrode connected to a first control node (Q); a second transistor comprising a first sub-transistor including a control electrode connected to a third control node (QB), a first electrode connected to the first intermediate node (NA) and a second electrode connected to the first control node (Q), and a second sub-transistor including a control electrode connected to the third control node (QB), a first electrode configured to receive a second low voltage (VGL2) and a second electrode connected to the first intermediate node (NA); a third transistor (T3) including a control electrode configured to receive a high voltage (VGH), a first electrode connected to the first control node (Q) and a second electrode connected to a second control node (QF); a fifth transistor (T5) including a control electrode connected to the second control node (QF), a first electrode configured to receive the high voltage (VGH) and a second electrode connected to a carry output terminal; a sixth transistor (T6) including a control electrode connected to the third control node (QB), a first electrode configured to receive the second low voltage (VGL2) and a second electrode connected to the carry output terminal; a seventh transistor (T7) including a control electrode connected to the second control node (QF), a first electrode configured to receive the high voltage (VGH) and a second electrode connected to a gate output terminal (OT[1] - OT[5]); and an eighth transistor (T8) including a control electrode connected to the third control node (QB), a first electrode configured to receive a first low voltage (VGL) and a second electrode connected to the gate output terminal (OT[1] - OT[5]).
  14. The electronic device (101, 102, 1000, 1000a, 1000b) of claim 13, wherein the gate driver (300, 300a, 300b, 300c) further comprises: a fourth (T4) transistor including a control electrode connected to the second control node (QF), a first electrode configured to receive a second clock signal (CLK2) and a second electrode connected to a second electrode of a first capacitor (C1), wherein the first capacitor (C1) includes a first electrode connected to the second control node (QF) and the second electrode and/or wherein the gate driver (300, 300a, 300b, 300c) further comprises a second capacitor (C2) including a first electrode connected to the second control node (QF) and a second electrode connected to the gate output terminal (OT[1] - OT[5]).
  15. The electronic device (101, 102, 1000, 1000a, 1000b) of claim 13, wherein the gate driver (300, 300a, 300b, 300c) further comprises: a ninth transistor comprising a first sub-transistor including a control electrode configured to receive the high voltage (VGH), a first electrode connected to a first node (NB) and a second electrode connected to a ninth intermediate node, and a second sub-transistor including a control electrode configured to receive the high voltage (VGH), a first electrode connected to the ninth intermediate node and a second electrode configured to receive the high voltage (VGH); and a tenth transistor (T10) including a control electrode connected to the first node, a first electrode configured to receive the high voltage (VGH) and a second electrode connected to the third control node (QB) and/or wherein the electronic device (101, 102, 1000, 1000a, 1000b) is configured as a display apparatus (10, 1060) and further comprising: a driving controller (200) configured to control the gate driver (300, 300a, 300b, 300c) and the data driver (143, 500); and a processor (110, 1010) configured to output input image data to the driving controller (200).

Description

FIELD Embodiments of the present inventive concept relate to a gate driver, a display apparatus including the gate driver and an electronic device including the gate driver. More particularly, embodiments of the present inventive concept relate to a gate driver with minimized power consumption, an electronic device including the gate driver, and a display apparatus including the gate driver or electronic device. INTRODUCTION A display apparatus may include a display panel and a display panel driver. The display panel may include a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver may include a gate driver, a data driver, an emission driver and a driving controller. The gate driver outputs gate signals to the gate lines. The data driver outputs data voltages to the data lines. The emission driver outputs emission signals to the emission lines. The driving controller controls the gate driver, the data driver and the emission driver. The display panel and the display panel driver may include P-type transistors and/or N-type transistors. To reduce or prevent a current leakage in the display panel, the display panel may include primarily N-type transistors. But even if the display panel includes exclusively N-type transistors while the gate driver of the display panel driver is integrated with the display panel and includes P-type transistors, a manufacturing process might be complex and/or current leakage might occur in the manufactured gate driver. In addition, a flicker might occur on the display panel due to the current leakage and diminish display quality of the display panel. When a clock signal is used as a gate output signal of the gate driver, power consumption might be high due to capacitance of a buffer transistor receiving the clock signal. In addition, when the gate driver is driven by a clock signal used as the gate output signal and a carry clock signal used as a carry signal of the gate driver, a size of the buffer transistor might be insufficient due to spatial limitations or the like so that a falling time of the gate output signal might be slow. When the falling time of the gate output signal is slow, a data voltage of another pixel might be incorrectly applied to a current pixel and diminish display quality of the display panel. SUMMARY Embodiments of the present inventive concept may provide a gate driver to maximize display quality and minimize power consumption. Embodiments of the present inventive concept may provide a display apparatus including the gate driver. Embodiments of the present inventive concept may provide an electronic device including the gate driver. In a gate driver according to an embodiment of the present inventive concept, the gate driver includes stages. A stage includes a first transistor having a 1-1 sub-transistor including a control electrode connected to a first clock signal line, a first electrode connected to an input signal line and a second electrode connected to a first intermediate node, and a 1-2 sub-transistor including a control electrode connected to the first clock signal line, a first electrode connected to the first intermediate node and a second electrode connected to a first control node, a second transistor having a 2-1 sub-transistor including a control electrode connected to a third control node, a first electrode connected to the first intermediate node and a second electrode connected to the first control node, and a 2-2 sub-transistor including a control electrode connected to the third control node, a first electrode connected to a second low voltage line and a second electrode connected to the first intermediate node, a third transistor including a control electrode connected to a high voltage line, a first electrode connected to the first control node and a second electrode connected to a second control node, a fifth transistor including a control electrode connected to the second control node, a first electrode connected to the high voltage line and a second electrode connected to a carry output terminal, a sixth transistor including a control electrode connected to the third control node, a first electrode connected to the second low voltage line and a second electrode connected to the carry output terminal, a seventh transistor including a control electrode connected to the second control node, a first electrode connected to the high voltage line and a second electrode connected to a gate output terminal and an eighth transistor including a control electrode connected to the third control node, a first electrode connected to a first low voltage line and a second electrode connected to the gate output terminal. In an embodiment, the stage may further include a fourth transistor including a control electrode connected to the second control node, a first electrode connected to a second clock signal line and a second electrode connected to a second electrod