EP-4738329-A1 - DRIVER, DISPLAY DEVICE INCLUDING DRIVER, AND ELECTRONIC DEVICE INCLUDING DRIVER

EP4738329A1EP 4738329 A1EP4738329 A1EP 4738329A1EP-4738329-A1

Abstract

A driver includes a first gate emission signal generator which generates a first driving signal; a second gate emission signal generator which generates a second driving signal; a clock line which is disposed between the first gate emission signal generator and the second gate emission signal generator and outputs a clock signal; and a low voltage line which is disposed between the first gate emission signal generator and the second gate emission signal generator and outputs a low voltage line. The first gate emission signal generator and the second gate emission signal generator are electrically connected to a same clock line. The first gate emission signal generator and the second gate emission signal generator are electrically connected to a same low voltage line.

Inventors

Cho, Jaehyung
LEE, DONG-HOON
JEONG, MINJAE
KIM, ILNAM
WOO, MINKYU
JANG, Jaeyong

Assignees

Samsung Display Co., Ltd.

Dates

Publication Date: 20260506
Application Date: 20251028

Claims (15)

A driver comprising: a first gate emission signal generator arranged to generate a first driving signal; a second gate emission signal generator arranged to generate a second driving signal different from the first driving signal, and wherein the second gate emission has a circuit structure substantially identical to a circuit structure of the first gate emission signal generator; a clock line which is disposed between the first gate emission signal generator and the second gate emission signal generator, wherein the clock line is arranged to output a clock signal; and a low voltage line which is disposed between the first gate emission signal generator and the second gate emission signal generator, wherein the low voltage line is arranged to output a first low gate voltage, wherein: the first gate emission signal generator is electrically connected to the clock line and the low voltage line, and the second gate emission signal generator is electrically connected to the clock line and the low voltage line to which the first gate emission signal generator is electrically connected.
The driver of claim 1, wherein the driver comprises a plurality of stages disposed in a direction, the first gate emission signal generator comprises a plurality of first gate emission signal generators; the second gate emission signal generator comprises a plurality of second gate emission signal generators; each of the plurality of stages comprises: a corresponding first gate emission signal generator among the plurality of first gate emission signal generators; and a corresponding second gate emission signal generator among the plurality of second gate emission signal generators, and the clock line comprises: a first clock line electrically connected to stages of the plurality of stages, which are disposed at odd-numbered rows; and a second clock line electrically connected to stages of the plurality of stages, which are disposed at even-numbered rows.
The driver of claim 2, wherein the low voltage line is disposed between the first clock line and the second clock line in a plan view.
The driver of claim 2 or 3, wherein the low voltage line, the first clock line, and the second clock line are disposed in a same layer.
The driver of claim 2 or 3, wherein the low voltage line is disposed in a different layer from the first clock line and the second clock line.
The driver of claim 5, wherein the low voltage line at least partially overlaps the first clock line or the second clock line in a plan view; and/or wherein the low voltage line is disposed under the first clock line and the second clock line.
The driver of any one of claims 1 to 6, wherein the first gate emission signal generator and the second gate emission signal generator are line-symmetrical with respect to the low voltage line.
The driver of any one of claims 1 to 7, wherein each of the first gate emission signal generator and the second gate emission signal generator comprises: an input circuit arranged to output an input signal to a control node in response to the clock signal; an inversion circuit arranged to invert a voltage of the control node, and arranged to output the inverted voltage to an inversion control node; a carry signal output circuit arranged to output the first low gate voltage to a carry output node in response to the voltage of the control node, and arranged to output a high gate voltage to the carry output node in response to a voltage of the inversion control node; and a driving signal output circuit arranged to output a second low gate voltage different from the first low gate voltage to a driving output node in response to the voltage of the control node, and arranged to output the high gate voltage to the driving output node in response to the voltage of the inversion control node.
The driver of claim 8, wherein the second low gate voltage is lower than the first low gate voltage.
A display device comprising: a display panel comprising a pixel; and a driver arranged to output a driving signal to the pixel, wherein the driver is according to any one of claims 1 to 9.
The display device of claim 10, wherein the display panel comprises: a pixel active pattern disposed on a substrate; a pixel gate electrode disposed on the pixel active pattern; a first pixel output electrode disposed on the pixel gate electrode; a second pixel output electrode disposed on the pixel gate electrode; a connection electrode disposed on the first pixel output electrode and the second pixel output electrode; and a light-emitting element which is disposed on the connection electrode and emits light.
The display device of claim 11, wherein the low voltage line, the clock line, and the connection electrode are disposed in a same layer; or wherein the low voltage line, the first pixel output electrode, and the second pixel output electrode are disposed in a same layer, and the clock line and the connection electrode are disposed in a same layer.
The display device of any one of claims 10 to 12, wherein the pixel comprises: a light-emitting element arranged to emit light; a first pixel transistor which provides a driving current to the light-emitting element; a second pixel transistor arranged to provide a data voltage to the first pixel transistor in response to a write gate signal; a third pixel transistor arranged to diode-connect the first pixel transistor in response to a compensation gate signal; a fourth pixel transistor arranged to provide a first initialization voltage to a gate electrode of the first pixel transistor in response to an initialization gate signal; a fifth pixel transistor arranged to provide a driving voltage to the first pixel transistor in response to an emission signal; a sixth pixel transistor arranged to electrically connect the first pixel transistor and the light-emitting element in response to the emission signal; and a seventh pixel transistor arranged to provide a second initialization voltage to a first electrode of the light-emitting element in response to a bias gate signal; optionally wherein the first driving signal is a driving signal selected from a group consisting of the emission signal, the compensation gate signal, the initialization gate signal, and the bias gate signal, and the second driving signal is different from the first driving signal and is a driving signal selected from the group consisting of the emission signal, the compensation gate signal, the initialization gate signal, and the bias gate signal.
The display device of claim 13, wherein the driver comprises: a first driver; and a second driver spaced apart from the first driver, the first gate emission signal generator comprises a plurality of first gate emission signal generators, the second gate emission signal generator comprises a plurality of second gate emission signal generators, each of the first driver and the second driver comprises: a corresponding first gate emission signal generator among the plurality of first gate emission signal generators; and a corresponding second gate emission signal generator among the plurality of second gate emission signal generators, the first driving signal of the first driver is the emission signal, the second driving signal of the first driver is a gate signal selected from a group consisting of the compensation gate signal, the initialization gate signal, and the bias gate signal, the first driving signal of the second driver is different from the second driving signal of the first driver and is a gate signal selected from the group consisting of the compensation gate signal, the initialization gate signal, and the bias gate signal, and the second driving signal of the second driver is a gate signal different from the second driving signal of the first driver and the first driving signal of the second driver.
An electronic device comprising: a display device as set out in any one of claims 10 to 14; a controller arranged to output a control signal to the driver; and a processor arranged to output an input image data and an input signal to the controller.

Description

BACKGROUND 1. Technical Field The disclosure relates to a driver for driving a display panel, a display device including the driver, and an electronic device including the driver. 2. Description of the Related Art The importance of display devices as communication media, has been emphasized because of the increasing developments of information technology. For example, users of display devices such as liquid crystal display (LCD) device, organic light emitting diode (OLED) display device, plasma display panel (PDP) device, quantum dot display device or the like have been increasing and becoming more popular. The display device may include a display panel and a driver that drives the display panel. The display panel may include gate lines, data lines, emission lines, and pixels. The driver may include a gate driver for providing a gate signal to the gate lines, a data driver for providing a data voltage to the data lines, an emission driver for providing an emission signal to the emission lines, and a controller for controlling the gate driver, the data driver, and the emission driver. In general, the display device may include a clock line and a voltage transfer line that are connected to the gate driver and the emission driver. As the number of the clock line and the number of the voltage transfer line increases, the integration of the driver may decrease. It is to be understood that this background of the technology section is, in part, intended to provide useful background for understanding the technology. However, this background of the technology section may also include ideas, concepts, or recognitions that were not part of what was appreciated by those skilled in the pertinent art prior to a corresponding effective filing date of the subject matter disclosed herein. SUMMARY Embodiments provide a driver with improved integration. Embodiments also provide a display device including the driver. Embodiments also provide an electronic device including the driver. However, embodiments of the disclosure are not limited to those set forth herein. The above and other embodiments will become more apparent to one of ordinary skill in the art to which the disclosure pertains by referencing the detailed description of the disclosure given below. A driver according to an embodiment of the disclosure includes: a first gate emission signal generator which generates a first driving signal; a second gate emission signal generator which generates a second driving signal different from the first driving signal and has a circuit structure substantially identical to a circuit structure of the first gate emission signal generator; a clock line which is disposed between the first gate emission signal generator and the second gate emission signal generator and outputs a clock signal; and a low voltage line which is disposed between the first gate emission signal generator and the second gate emission signal generator and outputs a first low gate voltage. The first gate emission signal generator is electrically connected to the clock line and the low voltage line. The second gate emission signal generator is electrically connected to the clock line and the low voltage line to which the first gate emission signal generator is electrically connected. In an embodiment, the driver may include a plurality of stages disposed in a direction. The first gate emission signal generator may include a plurality of first gate emission signal generators. The second gate emission signal generator may include a plurality of second gate emission signal generators. Each of the plurality of stages may include a corresponding first gate emission signal generator among the plurality of first gate emission signal generators and a corresponding second gate emission signal generator among the plurality of second gate emission signal generators. The clock line may include a first clock line electrically connected to stages of the plurality of stages, which are disposed at odd-numbered rows, and a second clock line electrically connected to stages of the plurality of stages, which are disposed at even-numbered rows. In an embodiment, the low voltage line may be disposed between the first clock line and the second clock line in a plan view. In an embodiment, the low voltage line, the first clock line, and the second clock line may be disposed in a same layer. In an embodiment, the low voltage line may be disposed in a different layer from the first clock line and the second clock line. In an embodiment, the low voltage line may at least partially overlap the first clock line or the second clock line in a plan view. In an embodiment, the low voltage line may be disposed under the first clock line and the second clock line. In an embodiment, the first gate emission signal generator and the second gate emission signal generator may be line-symmetrical with respect to the low voltage line. In an embodiment, each of the first gate emission signal generator an