EP-4738330-A1 - DISPLAY PANEL AND DISPLAY DEVICE

EP4738330A1EP 4738330 A1EP4738330 A1EP 4738330A1EP-4738330-A1

Abstract

A pixel circuit, a display panel, and a display device, relating to the technical field of display. The pixel circuit comprises a driving transistor (T3), an energy storage circuit (RU), a write circuit (DU), and a first light emission control circuit (EU1). A gate of the driving transistor (T3) is connected to a first electrode of the driving transistor (T3) by means of the energy storage circuit (RU); the first electrode of the driving transistor (T3) is adapted to be connected to a light-emitting device (LD); a second electrode of the driving transistor (T3) is connected to the first light emission control circuit (EU1); the first light emission control circuit (EU1) is used for receiving a first power supply signal (VDD); the write circuit is connected to the gate of the driving transistor (T3); the write circuit (DU) is connected to the first electrode of the driving transistor (T3) by means of the energy storage circuit (RU); the write circuit (DU) is used for writing a data signal (Data) to the energy storage circuit (RU); the energy storage circuit (RU) is used for storing the data signal (Data) and a voltage of the first electrode of the driving transistor (T3).

Inventors

HUANG, Yao
LEE, ANSU
DONG, Xiangdan
HU, MING

Assignees

Boe Technology Group Co., Ltd.
Chengdu BOE Optoelectronics Technology Co., Ltd.
Beijing BOE Technology Development Co., Ltd.

Dates

Publication Date: 20260506
Application Date: 20231229

Claims (20)

A pixel circuit, comprising a driving transistor, an energy storage circuit, a writing circuit and a first light emitting control circuit; a gate of the driving transistor is connected to a first electrode of the driving transistor through the energy storage circuit, the first electrode of the driving transistor is configured to be connected to a light emitting device, and a second electrode of the driving transistor is connected to the first light emitting control circuit, and the first light emitting control circuit is configured to receive a first power signal; and the writing circuit is connected to the gate of the driving transistor, the writing circuit is connected to the first electrode of the driving transistor through the energy storage circuit, the writing circuit is configured to write a data signal to the energy storage circuit, and the energy storage circuit is configured to store the data signal and a voltage of the first electrode of the driving transistor.
The pixel circuit according to claim 1, wherein the energy storage circuit comprises a first capacitor and a second capacitor, the writing circuit comprises a writing transistor, and the first light emitting control circuit comprises a first light emitting control transistor; a first electrode of the writing transistor is configured to input the data signal, and a second electrode of the writing transistor is connected to the gate of the driving transistor and a first plate of the first capacitor; a second plate of the first capacitor is connected to a first plate of the second capacitor, and a second plate of the second capacitor is connected to the first electrode of the driving transistor; and a first electrode of the first light emitting control transistor is configured to input the first power signal, and a second electrode of the first light emitting control transistor is connected to the second electrode of the driving transistor.
The pixel circuit according to claim 2, wherein the pixel circuit further comprises: a first reset transistor, wherein a first electrode of the first reset transistor is configured to receive a reference signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor; and a second reset transistor, wherein a first electrode of the second reset transistor is configured to receive the reference signal, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor.
The pixel circuit according to claim 3, wherein the pixel circuit further comprises: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second plate of the second capacitor.
The pixel circuit according to claim 3, wherein the pixel circuit further comprises a second light emitting control circuit, and the first electrode of the driving transistor is connected to the light emitting device through the second light emitting control circuit.
The pixel circuit according to claim 5, wherein the second light emitting control circuit comprises a second light emitting control transistor, a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor, and a second electrode of the second light emitting control transistor is connected to the light emitting device; and the pixel circuit further comprises: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor.
The pixel circuit according to claim 6, wherein at least one of the driving transistor, the writing transistor, the first reset transistor, the second reset transistor, the third reset transistor, the first light emitting control transistor, and the second light emitting control transistor is a metal oxide transistor.
A display panel, comprising a plurality of pixel circuits arranged in an array along a row direction and a column direction, wherein the pixel circuit comprises a plurality of transistors, a first capacitor and a second capacitor, and individual transistors comprises a driving transistor, a writing transistor, a first light emitting control transistor, a second light emitting control transistor, a first reset transistor, a second reset transistor and a third reset transistor; a first electrode of the first light emitting control transistor is configured to receive a first power signal, and a second electrode of the first light emitting control transistor is connected to a second electrode of the driving transistor; a first electrode of the writing transistor is configured to receive a data signal, a second electrode of the writing transistor is connected to a first plate of the first capacitor and a gate of the driving transistor, a second plate of the first capacitor is connected to a first plate of the second capacitor, and a second plate of the second capacitor is connected to a first electrode of the driving transistor; a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor; a first electrode of the first reset transistor and a first electrode of the second reset transistor are configured to receive a reference signal, a second electrode of the first reset transistor is connected to the gate of the driving transistor, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor; a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor or the second electrode of the second light emitting control transistor; the display panel comprises: a substrate; a semiconductor layer, disposed on a side of the substrate and comprising an active portion of each of the transistors; a plurality of light emitting devices, disposed on a side of the semiconductor layer away from the substrate, wherein a light emitting device is connected to a second electrode of a second light emitting control transistor of a pixel circuit; and one of the first plate and the second plate of the first capacitor is disposed in the same layer as one of the first plate and the second plate of the second capacitor, and one of the first capacitor and the second capacitor is overlapped with an active portion of the driving transistor.
The display panel according to claim 8, wherein the semiconductor layer comprises a first semiconductor portion and a second semiconductor portion distributed at an interval along the row direction; and active portions of the writing transistor, the first reset transistor and the second reset transistor are located in the first semiconductor portion and are connected in sequence, and active portions of the first light emitting control transistor, the driving transistor, the second light emitting control transistor and the third reset transistor are located in the second semiconductor portion and are connected in sequence.
The display panel according to claim 9, wherein the first plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the second plate of the first capacitor and the second plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; and the first plate and the second plate of the second capacitor are overlapped with the active portion of the driving transistor.
The display panel according to claim 9, wherein the first plate of the first capacitor and the second plate of the second capacitor are disposed in the same layer and are distributed at an interval along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are disposed in the same layer and are connected into an integrated structure; and the first plate and the second plate of the second capacitor are overlapped with the active portion of the driving transistor.
The display panel according to claim 8, wherein an active portion of the first light emitting control transistor is overlapped with the first plate and the second plate of the first capacitor.
The display panel according to claim 10, wherein the first semiconductor portion comprises a first semiconductor segment, a second semiconductor segment and a third semiconductor segment; the first semiconductor segment and the third semiconductor segment are extended along the column direction and are distributed at an interval along the row direction, and the second semiconductor segment is connected to the first semiconductor segment and the third semiconductor segment; the active portions of the writing transistor and the first reset transistor are located in the first semiconductor segment, the active portion of the second reset transistor is located in the second semiconductor segment, and the third semiconductor segment is connected to the first plate of the second capacitor.
The display panel according to claim 13, wherein the second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the first electrode of the second light emitting control transistor; the second semiconductor portion comprises a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment is extended along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment, and the active portions of the first light emitting control transistor, the driving transistor and the second light emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction; and the fifth semiconductor segment is connected to an area of the fourth semiconductor segment between the active portion of the driving transistor and the active portion of the second light emitting control transistor, and the active portion of the third reset transistor is located in the fifth semiconductor segment.
The display panel according to claim 13, wherein the second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor and the light emitting device; the second semiconductor portion comprises a fourth semiconductor segment and a fifth semiconductor segment, the fourth semiconductor segment is extended along the column direction and is located on a side of the third semiconductor segment away from the first semiconductor segment, and the active portions of the first light emitting control transistor, the driving transistor and the second light emitting control transistor are sequentially distributed in the fourth semiconductor segment along the column direction; and the fifth semiconductor segment is connected to an area of the fourth semiconductor segment on a side of the active portion of the second light emitting control transistor away from the active portion of the driving transistor, and the active portion of the third reset transistor is located in the fifth semiconductor segment.
The display panel according to claim 10, wherein the display panel further comprises a first light emitting control line, a scan line, a first reset control line, a first reset line, a second reset control line, a second light emitting control line, a third reset control line and a second reset line sequentially distributed at intervals along the column direction; the first light emitting control line is extended along the row direction, is connected to a gate of the first light emitting control transistor, and is configured to transmit a first light emitting control signal, and the first light emitting control line is overlapped with the first capacitor; the scan line is extended along the row direction, is connected to a gate of the writing transistor, and is configured to transmit a scan signal, and the scan line is overlapped with the first capacitor; the first reset control line is extended along the row direction, is connected to a gate of the first reset transistor, and is configured to transmit a first reference control signal, and the first reset control line is overlapped with the second capacitor; the first reset line is extended along the row direction, is connected to first electrodes of the first reset transistor and the second reset transistor, and is configured to transmit the reference signal, and the first reset line is overlapped with the second capacitor; the second reset control line is extended along the row direction, is connected to a gate of the second reset transistor, and is configured to transmit a second reference control signal; the second light emitting control line is extended along the row direction, is connected to a gate of the second light emitting control transistor, and is configured to transmit a second light emitting control signal; the third reset control line is extended along the row direction, is connected to a gate of the third reset transistor, and is configured to transmit a reset control signal; the second reset line is extended along the row direction, is connected to the first electrode of the third reset transistor, and is configured to transmit the reset signal; an orthographic projection of the active portion of the driving transistor on the substrate is located between orthographic projections of the scan line and the first reset control line on the substrate; an orthographic projection of the active portion of the first reset transistor on the substrate is located between orthographic projections of the scan line and the first reset line on the substrate; an orthographic projection of the active portion of the second reset transistor on the substrate is located between orthographic projections of the first reset line and the second light emitting control line on the substrate; and an orthographic projection of the active portion of the third reset transistor on the substrate is located between orthographic projections of the second light emitting control line and the second reset line on the substrate.
The display panel according to claim 16, wherein the display panel further comprises: a plurality of first auxiliary power lines, extended along the row direction and distributed along the column direction, wherein a first auxiliary power line is disposed between two adjacent rows of pixel circuits, and the first auxiliary power line is connected to a first electrode of a first light emitting control transistor of a pixel circuit on a side of the first auxiliary power line; a plurality of first power lines, disposed on a side of the first auxiliary power lines away from the substrate, wherein individual first power lines are extended along the column direction and are distributed at intervals along the row direction, a first power line is connected to individual first auxiliary power lines and is overlapped with a column of pixel circuits, and the first power lines and the first auxiliary power lines are configured to transmit the first power signal; and a plurality of data lines, disposed on the side of the first auxiliary power lines away from the substrate, wherein individual data lines are extended along the column direction and are distributed at intervals along the row direction, and a data line is connected to first electrodes of writing transistors of a column of pixel circuits and is configured to transmit the data signal.
The display panel according to claim 17, wherein the display panel further comprises: a second auxiliary power line, extended along the row direction, distributed along the column direction, and configured to transmit a second power signal, wherein an orthographic projection of the second auxiliary power line on the substrate is located between orthographic projections of the second light emitting control line and the third reset control line on the substrate.
The display panel according to claim 18, wherein the display panel further comprises: a plurality of second power lines, a plurality of first auxiliary reset lines, and a plurality of second auxiliary reset lines, extended along the column direction and distributed along the row direction, and disposed on the side of the first auxiliary power lines away from the substrate, wherein the second power line is connected to the second auxiliary power line, the first auxiliary reset line is connected to the first reset line, and the second auxiliary reset line is connected to the second reset line; a first power line and a data line connected to pixel circuits in the same column are defined as a column line group, and the first power line and the data line of the column line group are provided with one of the second power line, the first auxiliary reset line and the second auxiliary reset line; and the light emitting device has a first electrode and a second electrode distributed in a direction away from the substrate, the first electrode is connected to the second electrode of the second light emitting control transistor, and the second electrode is connected to the second power line and the second auxiliary power line.
The display panel according to claim 19, wherein the semiconductor layer further comprises a first auxiliary transfer portion and a second auxiliary transfer portion; the first auxiliary transfer portion is connected to an area of a first semiconductor portion of a pixel circuit between the active portion of the first reset transistor and the active portion of the second reset transistor, and the first auxiliary reset line is connected to the first auxiliary transfer portion; and the second auxiliary transfer portion is connected to an area of a second semiconductor portion of a pixel circuit on a side of the active portion of the third reset transistor away from the active portion of the second light emitting control transistor, and the second auxiliary reset line is connected to the second auxiliary transfer portion.

Description

TECHNICAL FIELD The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device. BACKGROUND Organic Light Emitting Diode (OLED) display panels have the advantages of self-luminescence, wide color gamut, high contrast, flexibility, high response and flexibility, etc., and have broad application prospects. However, the uniformity of the luminous brightness of the existing display panels still needs to be improved, and display screen abnormalities are prone to occur. It should be noted that the information disclosed in the Background section above is only for enhancing the understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY An objective of the present disclosure is to overcome the above-mentioned deficiencies in the prior art and provide a display panel and a display device. According to an aspect of the present disclosure, there is provided a pixel circuit, including a driving transistor, an energy storage circuit, a writing circuit and a first light emitting control circuit; a gate of the driving transistor is connected to a first electrode of the driving transistor through the energy storage circuit, the first electrode of the driving transistor is configured to be connected to a light emitting device, and a second electrode of the driving transistor is connected to the first light emitting control circuit, and the first light emitting control circuit is configured to receive a first power signal; andthe writing circuit is connected to the gate of the driving transistor; the writing circuit is connected to the first electrode of the driving transistor through the energy storage circuit; the writing circuit is configured to write a data signal to the energy storage circuit; the energy storage circuit is configured to store the data signal and a voltage of the first electrode of the driving transistor. In an embodiment of the present disclosure, the energy storage circuit includes a first capacitor and a second capacitor; the writing circuit includes a writing transistor; the first light emitting control circuit includes a first light emitting control transistor; a first electrode of the writing transistor is configured to input the data signal, and a second electrode of the writing transistor is connected to the gate of the driving transistor and a first plate of the first capacitor; a second plate of the first capacitor is connected to the first plate of the second capacitor, and a second plate of the second capacitor is connected to the first electrode of the driving transistor; a first electrode of the first light emitting control transistor is configured to input the first power signal, and a second electrode of the first light emitting control transistor is connected to the second electrode of the driving transistor. In an embodiment of the present disclosure, the pixel circuit further includes: a first reset transistor, wherein a first electrode of the first reset transistor is configured to receive a reference signal, and a second electrode of the first reset transistor is connected to the gate of the driving transistor; anda second reset transistor, wherein a first electrode of the second reset transistor is configured to receive the reference signal, and a second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor. In an embodiment of the present disclosure, the pixel circuit further includes: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second plate of the second capacitor. In an embodiment of the present disclosure, the pixel circuit further includes a second light emitting control circuit, and the first electrode of the driving transistor is connected to the light emitting device through the second light emitting control circuit. In an embodiment of the present disclosure, the second light emitting control circuit includes a second light emitting control transistor; a first electrode of the second light emitting control transistor is connected to the first electrode of the driving transistor, and a second electrode of the second light emitting control transistor is connected to the light emitting device; the pixel circuit further inlcudes: a third reset transistor, wherein a first electrode of the third reset transistor is configured to receive a reset signal, and a second electrode of the third reset transistor is connected to the second electrode of the second light emitting control transistor. In an embodiment of the present disclosure, at least one of the driving transistor, the writing transistor, the first reset trans