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EP-4738332-A1 - PIXEL OF A DISPLAY DEVICE, DISPLAY DEVICE AND ELECTRONIC DEVICE

EP4738332A1EP 4738332 A1EP4738332 A1EP 4738332A1EP-4738332-A1

Abstract

A pixel (100) of a display device includes a first transistor (T1) having a first gate connected to a first node (N1), a first terminal receiving a first power supply voltage (ELVDD), and a second terminal connected to a second node (N2). A first capacitor (CST) is connected between the first and second nodes. A second capacitor (CHOLD) is connected between the first power supply voltage and the second node. A second transistor (T2) transfers a data voltage to the first node. A third transistor (T3) selectively connects the second node to an anode electrode of a light-emitting element (EL) based on a first emission signal (EM1). In a first mode, during data writing, the third transistor is turned off, and the first transistor generates an emission current independent of the capacitance of the light-emitting element (CEL). In a second mode, the third transistor is turned on, and the emission current depends on the capacitance of the light-emitting element.

Inventors

  • SHIM, JONGSIK
  • KIM, AHYOUNG
  • Yang, Chanyoung
  • LEE, SEONGKYU

Assignees

  • Samsung Display Co., Ltd.

Dates

Publication Date
20260506
Application Date
20250702

Claims (20)

  1. A pixel (100) of a display device (700), the pixel (100) comprising: a first transistor (T1) including a first gate connected to a first node (N1), a first terminal configured to receive a first power supply voltage (ELVDD), and a second terminal connected to a second node (N2); a first capacitor (CST) including a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2); a second capacitor (CHOLD) including a first electrode configured to receive the first power supply voltage (ELVDD), and a second electrode connected to the second node (N2); a second transistor (T2) including a gate configured to receive a first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node (N1); a light-emitting element including an anode electrode, and a cathode electrode configured to receive a second power supply voltage (ELVSS); and a third transistor (T3) including a gate configured to receive a first emission signal (EM1), a first terminal connected to the second node (N2), and a second terminal connected to the anode electrode, the third transistor (T3) configured to be turned off while the second transistor (T2) is turned on in a first mode, and to be turned on while the second transistor (T2) is turned on in a second mode.
  2. The pixel (100) of claim 1, wherein, during a data writing period (PDW@M1) of the first mode, the second electrode of the first capacitor (CST) is connected to the second capacitor (CHOLD), and is separated from the anode electrode, and wherein, during a data writing period (PDW@M1) of the second mode, the second electrode of the first capacitor (CST) is connected to the second capacitor (CHOLD) and the anode electrode.
  3. The pixel (100) of claim 1 or 2, wherein, during an emission period (PEM@M1) of the first mode, the first transistor (T1) generates an emission current based on a voltage independently of a capacitance of the light-emitting element, and wherein, during an emission period (PEM@M1) of the second mode, the first transistor (T1) generates an emission current based on a voltage stored in the first capacitor (CST) and dependent upon the capacitance.
  4. The pixel (100) of at least one of claims 1 to 3, wherein, with respect to a same data voltage, an emission current generated by the first transistor (T1) in the first mode is less than an emission current generated by the first transistor (T1) in the second mode.
  5. The pixel (100) of at least one of claims 1 to 4, wherein an emission current generated by the first transistor (T1) in the first mode is determined by an equation "IEL = K Chold Cst + Chold VDAT − VREF 2 , and wherein an emission current generated by the first transistor (T1) in the second mode is determined by an equation " IEL = K Chold + Cel Cst + Chold + Cel VDAT − VREF 2 ", where IEL is an emission current generated by the first transistor (T1), K is a current coefficient, Cst is a capacitance of the first capacitor (CST), Chold is a capacitance of the second capacitor (CHOLD), VDAT is a data voltage, VREF is a reference voltage (VREF), and Cel is a capacitance of the light-emitting element.
  6. The pixel (100) of at least one of claims 1 to 5, wherein the first mode is a normal mode and the second mode is a high brightness mode.
  7. The pixel (100) of at least one of claims 1 to 6, wherein the first transistor (T1) is an N-type metal-oxide-semiconductor transistor.
  8. The pixel (100) of at least one of claims 1 to 7, wherein the first transistor (T1) further includes a second gate connected to the second node (N2).
  9. The pixel (100) of at least one of claims 1 to 8, further comprising: a fourth transistor (T4) including a gate configured to receive a second gate signal, a first terminal configured to receive a reference voltage (VREF), and a second terminal connected to the first node (N1); a fifth transistor (T5) including a gate configured to receive a third gate signal (GI), a first terminal configured to receive an initialization voltage (VINT), and a second terminal connected to the anode electrode; and a sixth transistor (T6) including a gate configured to receive a second emission signal (EM2), a first terminal configured to receive the first power supply voltage (ELVDD), and a second terminal connected to the first terminal of the first transistor (T1).
  10. The pixel (100) of claim 9, wherein the first, second, third, fourth and fifth transistors (T1, T2, T3, T4, T5) are N-type metal-oxide-semiconductor transistors, and wherein the sixth transistor (T6) is a P-type metal-oxide-semiconductor transistor.
  11. The pixel (100) of claim 9 or 10, wherein a frame period (FP) for the pixel (100) of the display device (700) includes: an initialization period (PINI) in which the first node (N1) and the second node (N2) are initialized; a compensation period (PCMP) in which a threshold voltage of the first transistor (T1) is stored in the first capacitor (CST); a data writing period (PDW@M1) in which a data voltage is transferred to the first node (N1); and an emission period (PEM@M1) in which the light-emitting element emits light.
  12. The pixel (100) of claim 11, wherein, in the first mode, the third transistor (T3) is turned off in the compensation period (PCMP) and the data writing period (PDW@M1), and is turned on in the initialization period (PINI) and the emission period (PEM@M1), and wherein, in the second mode, the third transistor (T3) is turned off in the compensation period (PCMP), and is turned on in the initialization period (PINI), the data writing period (PDW@M1) and the emission period (PEM@M1).
  13. The pixel (100) of claim 11 or 12, wherein, in the first mode, the third transistor (T3) is turned off in the compensation period (PCMP) and the data writing period (PDW@M1), and is turned on in the initialization period (PINI) and the emission period (PEM@M1), and wherein, in the second mode, the third transistor (T3) is turned on in an entire period of the frame period (FP).
  14. The pixel (100) of at least one of claims 11 to 13, wherein, in each of the first mode and the second mode, the fifth transistor (T5) is turned off in the compensation period (PCMP), the data writing period (PDW@M1) and the emission period (PEM@M1), and is turned on in the initialization period (PINI).
  15. The pixel (100) of at least one of claims 11 to 14, wherein, in the first mode, the fifth transistor (T5) is turned off in the emission period (PEM@M1), and is turned on in the initialization period (PINI), the compensation period (PCMP) and the data writing period (PDW@M1), and wherein, in the second mode, the fifth transistor (T5) is turned off in the compensation period (PCMP), the data writing period (PDW@M1) and the emission period (PEM@M1), and is turned on in the initialization period (PINI).
  16. The pixel (100) of at least one of claims 11 to 15, wherein the frame period (FP) further includes: an anode initialization period (PINI@M1) in which the anode electrode is initialized.
  17. The pixel (100) of claim 16, wherein, in each of the first mode and the second mode, the anode initialization period (PINI@M1) is between the data writing period (PDW@M1) and the emission period (PEM@M1).
  18. The pixel (100) of claim 16 or 17, wherein, in the first mode, the anode initialization period (PINI@M1) overlaps the compensation period (PCMP) and the data writing period (PDW@M1), and wherein, in the second mode, the anode initialization period (PINI@M1) is between the data writing period (PDW@M1) and the emission period (PEM@M1).
  19. A display device (700) comprising: a display panel (710) including a plurality of pixels (100), including in particular at least one pixel of at least one of claims 1 to 18; a data driver (720) configured to provide a data voltage to each of the plurality of pixels (100); a scan driver (730) configured to provide a first gate signal to each of the plurality of pixels (100); an emission driver (740) configured to provide a first emission signal (EM1) to each of the plurality of pixels (100); and a controller (750) configured to receive a mode signal (SMODE), and to control the data driver (720), the scan driver (730) and the emission driver, wherein each of the plurality of pixels (100) comprises: a first transistor (T1) including a first gate connected to a first node (N1), a first terminal configured to receive a first power supply voltage (ELVDD), and a second terminal connected to a second node (N2); a first capacitor (CST) including a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2); a second capacitor (CHOLD) including a first electrode configured to receive the first power supply voltage (ELVDD), and a second electrode connected to the second node (N2); a second transistor (T2) including a gate configured to receive the first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node (N1); a light-emitting element including an anode electrode, and a cathode electrode configured to receive a second power supply voltage (ELVSS); and a third transistor (T3) including a gate configured to receive the first emission signal (EM1), a first terminal connected to the second node (N2), and a second terminal connected to the anode electrode, wherein, when the mode signal (SMODE) indicates a first mode, the third transistor (T3) is turned off while the data voltage is applied to the first node (N1) through the data line and the second transistor (T2), and wherein, when the mode signal (SMODE) indicates a second mode, the third transistor (T3) is turned on while the data voltage is applied to the first node (N1) through the data line and the second transistor (T2).
  20. An electronic device comprising: a processor (1110) configured to provide input image data and a mode signal (SMODE); and a display device (700), in particular a display device of claim 19, including a plurality of pixels (100), in particular at least one pixel of at least one of claims 1 to 18, the display device (700) is configured to receive the input image data and the mode signal (SMODE), and to drive the plurality of pixels (100) based on the input image data and the mode signal (SMODE), wherein each of the plurality of pixels (100) comprises: a first transistor (T1) including a first gate connected to a first node (N1), a first terminal configured to receive a first power supply voltage (ELVDD), and a second terminal connected to a second node (N2); a first capacitor (CST) including a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2); a second capacitor (CHOLD) including a first electrode configured to receive the first power supply voltage (ELVDD), and a second electrode connected to the second node (N2); a second transistor (T2) including a gate configured to receive a first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node (N1); a light-emitting element including an anode electrode, and a cathode electrode configured to receive a second power supply voltage (ELVSS); and a third transistor (T3) including a gate configured to receive a first emission signal (EM1), a first terminal connected to the second node (N2), and a second terminal connected to the anode electrode, wherein, when the mode signal (SMODE) indicates a first mode, the third transistor (T3) is turned off while the data voltage is applied to the first node (N1) through the data line and the second transistor (T2), and wherein, when the mode signal (SMODE) indicates a second mode, the third transistor (T3) is turned on while the data voltage is applied to the first node (N1) through the data line and the second transistor (T2).

Description

1. Technical Field Embodiments of the present inventive concept are directed to a display device, and more particularly to a pixel of a display device, the display device and an electronic device. 2. Discussion of Related Art Modern display devices are electronic screens used to visually present information, images, or videos. These devices include technologies such as Liquid Crystal Display (LCD), Light Emitting Diode (LED), Organic LED (OLED), and MicroLED. Modern displays focus on high resolution, fast refresh rates, touch sensitivity, and thin, flexible form factors. A pixel (short for picture element) is the smallest unit of a digital image or display. In modern displays like LCD, OLED, or LED screens, a pixel is a tiny dot that can emit or control light to show a specific color. The pixel may include a storage capacitor, a scan transistor that transfers a data voltage to the storage capacitor in response to a scan signal, a driving transistor that generates an emission current based on the data voltage stored in the storage capacitor, and a light-emitting element that emits light based on the emission current. The driving transistor is typically implemented with a low-temperature polycrystalline silicon ("LTPS") transistor. However, to enhance image quality, pixels using oxide transistors for the driving transistor have been recently developed. While oxide transistors can enhance image quality, they exhibit greater current fluctuation in response to voltage fluctuations compared to the LTPS transistor. As a result, a luminance sensitivity of a pixel including the oxide transistor as the driving transistor may be higher than that a pixel including the LTPS transistor as the driving transistor. SUMMARY Some embodiments provide a pixel of a display device capable of enhancing or reducing a luminance sensitivity in response to voltage fluctuations, a display device including the pixel, and an electronic device including the display device. The invention is defined by the independent claims. Preferred embodiments are disclosed by the dependent claims. According to one aspect of the invention, there is provided a pixel of a display device. The pixel includes a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power supply voltage, and a second terminal connected to a second node, a first capacitor including a first electrode connected to the first node, and a second electrode connected to the second node, a second capacitor including a first electrode configured to receive the first power supply voltage, and a second electrode connected to the second node, a second transistor including a gate configured to receive a first gate signal, a first terminal connected to a data line, and a second terminal connected to the first node, a light-emitting element including an anode electrode, and a cathode electrode configured to receive a second power supply voltage, and a third transistor including a gate configured to receive a first emission signal, a first terminal connected to the second node, and a second terminal connected to the anode electrode, the third transistor configured to be turned off while the second transistor is turned on in a first mode, and to be turned on while the second transistor is turned on in a second mode. In embodiments, during a data writing period of the first mode, the second electrode of the first capacitor may be connected to the second capacitor, and may be separated from the anode electrode. During a data writing period of the second mode, the second electrode of the first capacitor may be connected to the second capacitor and the anode electrode. In embodiments, during an emission period of the first mode, the first transistor may generate an emission current based on a voltage independently of a capacitance of the light-emitting element. During an emission period of the second mode, the first transistor may generate an emission current based on a voltage stored in the first capacitor and dependent upon the capacitance. In embodiments, with respect to a same data voltage, an emission current generated by the first transistor in the first mode may be less than an emission current generated by the first transistor in the second mode. In embodiments, an emission current generated by the first transistor in the first mode may be determined by an equation " IEL=KCholdCst+CholdVDAT−VREF2" and an emission current generated by the first transistor in the second mode may be determined by an equation "IEL = KChold+CelCst+Chold+CelVDAT−VREF2", where IEL is an emission current generated by the first transistor, K is a current coefficient, Cst is a capacitance of the first capacitor, Chold is a capacitance of the second capacitor, VDAT is a data voltage, VREF is a reference voltage, and Cel is a capacitance of the light-emitting element. In embodiments, the first mode may be a normal mode and the second mode may be a high brightn