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EP-4738335-A1 - DISPLAY DEVICE

EP4738335A1EP 4738335 A1EP4738335 A1EP 4738335A1EP-4738335-A1

Abstract

A display device (100) includes: a sub-pixel (SPij) connected to a data line (DLj), a first sub-gate line (SGL1), a second sub-gate line (SGL2), and a third sub-gate line (SGL3), and including a light-emitting element (LD) ; a gate driver (120) configured to supply a first sub-gate signal (GW) to the first sub-gate line (SGL1), a second sub-gate signal (GR) to the second sub-gate line (SGL2), and a third sub-gate signal (GI) to the third sub-gate line (SGL3) ; and a data driver (130) configured to supply a data voltage to the data line (DLj). A length of a period (P1) in which the third sub-gate signal (GI) is supplied during a display scan period is different from a length of a period (P2) in which the third sub-gate signal (GI) is supplied during a self-scan period. The third sub-gate signal (GI) is provided to control a time at which an electrode (AE) of the light-emitting element (LD) is initialized.

Inventors

  • KIM, BYUNG CHUL
  • HUH, JOON
  • LEE, SANG MYOUNG
  • KWON, OH CHUL
  • SONG, BYUNG KWAN
  • EOM, KI MYEONG
  • LEE, JAE HOON
  • CHA, KI SEOK
  • KANG, SANG HYUN
  • KIM, PAN JU

Assignees

  • Samsung Display Co., Ltd.

Dates

Publication Date
20260506
Application Date
20251104

Claims (15)

  1. The display device (100) comprising: a sub-pixel (SPij) connected to a data line (DLj), a first sub-gate line (SGL1), and a second sub-gate line (SGL2), and a third sub-gate line (SGL3) and including a light-emitting element (LD); a gate driver (120) configured to supply a first sub-gate signal (GW) to the first sub-gate line (SGL1), supply a second sub-gate signal (GR) to the second sub-gate line (SGL2), and supply a third sub-gate signal (GI) to the third sub-gate line (SGL3); and a data driver (130) configured to supply a data voltage to the data line (DLj), wherein a length of a period (P1) in which the third sub-gate signal (GI) is supplied during a display scan period is different from a length of a period (P2) in which the third sub-gate signal (GI) is supplied during a self-scan period; and wherein the third sub-gate signal (GI) is provided to control a time at which an electrode (AE) of the light-emitting element (LD) is initialized.
  2. The display device (100) of claim 1, wherein the sub-pixel (SPij) is further connected to a first sub-light emission control line (SEL1) and a second sub-light emission control line (SEL2), and wherein the sub-pixel (SPij) comprises: a first transistor (T1) configured to control driving current, the first transistor (T1) coupled between a first node (N1) which receives a first power supply voltage (VDDN) and a second node (N2) and including a gate electrode coupled to a third node (N3); a second transistor (T2) connected between the data line (DLj) and the third node (N3) and including a gate electrode connected to the first sub-gate line (SGL1); a sixth transistor (T6) connected between the second node (N2) and a fourth node (N4), and including a gate electrode connected to the second sub-light emission control line (SEL2); and a fourth transistor (T4) connected between a node configured to provide an initialization voltage (VINTN) and the fourth node (N4), and including a gate electrode connected to the third sub-gate line (SGL3), wherein the light-emitting element (LD) is connected between the fourth node (N4) and a node which receives a second power supply voltage (VSSN); and wherein the gate driver (120) is further configured to supply a first sub-light emission control signal (EM) to the first sub-light emission control line (SEL1) and a second sub-light emission control signal (EMB) to the second sub-light emission control line (SEL2).
  3. The display device (100) of any one of claims 1 and 2, wherein the data voltage is written to the sub-pixel (SPij) during the display scan period, and the data voltage is not written to the sub-pixel (SPij) during the self-scan period.
  4. The display device (100) of any one of claims 1 to 3, wherein: during the display scan period, the gate driver (120) is configured to supply the third sub-gate signal (GI) for a first period (P1); and during the self-scan period, the gate driver (120) is configured to supply the third sub-gate signal (GI) for a second period (P2).
  5. The display device (100) of claim 4, wherein a length of the first period (P1) is longer than a length of the second period (P2).
  6. The display device (100) of claim 5, wherein a length between an end time (t6) of a non-emission period (NEP) including the first period (P1) and an end time (t2) of the first period (P1) is the same as a length between an end time (t6) of a non-emission period (NEP) including the second period (P2) and an end time (t2) of the second period (P2).
  7. The display device (100) of claim 6, wherein a length between a start time (t5) of the non-emission period (NEP) including the first period (P1) and a start time (t1) of the first period (P1) is shorter than a length between a start time (t5) of the non-emission period (NEP) including the second period (P2) and a start time (t3) of the second period (P2).
  8. The display device (100) of claim 4, wherein a length of the first period (P1) is shorter than a length of the second period (P2).
  9. The display device (100) of claim 8, wherein a length between an end time (t6) of a non-emission period (NEP) including the first period (P1) and an end time (t2) of the first period (P1) is the same as a length between an end time (t6) of a non-emission period (NEP) including the second period (P2) and an end time (t2) of the second period (P2).
  10. The display device (100) of claim 9, wherein a length between a start time (t5) of the non-emission period (NEP) including the first period (P1) and a start time (t1) of the first period (P1) is longer than a length between a start time (t5) of the non-emission period (NEP) including the second period (P2) and a start time (t3) of the second period (P2).
  11. The display device (100) of claim 2, wherein the sub-pixel (SPij) further comprises: a fifth transistor (T5) connected between a node configured to receive the first power supply voltage (VDDN) and the first node (N1), and including a gate electrode connected to the first sub-light emission control line (SEL1); and a third transistor (T3) connected between a node configured to receive a reference voltage (VRFN) and the third node (N3), and including a gate electrode connected to the second sub-gate line (SGL2).
  12. The display device of any one of claims 1 to 11, further comprising a controller (150) configured to control the gate driver (120) based on a driving frequency of the display device.
  13. A method of operating the display device (100) of claim 1, the method comprising: supplying the third sub-gate signal (GI) for a first period (P1) during the display scan period; and supplying the third sub-gate signal (GI) for a second period (P2) during the self-scan period, wherein the length of the first period (P1) is different from the length of the second period (P2).
  14. The method of claim 13, wherein the length of the first period (P1) is longer than the length of the second period (P2), and wherein an end time (t2) of the first period (P1) and an end time of the second period (P2) occur at a same point in time relative to an end of a respective non-emission period (NEP).
  15. An electronic device (1000) comprising a processor (1010); and the display device (100; 1060) of any one of claims 1 to 12.

Description

BACKGROUND 1. Field Aspects of some embodiments of the present disclosure relate to a display device and an electronic device including the same. 2. Description of the Related Art With the development of information technology, the importance of display devices, which provide a connection medium between users and information, are being highlighted. Accordingly, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing. Display devices may include a plurality of pixels. A pixel column may be connected to the same data line. In this case, when the data voltage changes rapidly, it may affect other pixel rows in which the data voltage is not written. This may cause unintended image such as mura to be visually recognized in some areas of the display panel. The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art. SUMMARY Aspects of some embodiments of the present disclosure include a display device that minimizes or reduces stains and an electronic device including the same. The invention is defined by the appended set of claims. The description that follows is subjected to this limitation. Any disclosure lying outside the scope of said claims is only intended for illustrative as well as comparative purposes. According to some embodiments of the present disclosure, a display device includes a sub-pixel connected to a data line, a first sub-gate line, a second sub-gate line, and a third sub-gate line, and including a light-emitting element. The display device also includes a gate driver configured to supply a first sub-gate signal to the first sub-gate line, a second sub-gate signal to the second sub-gate line, and a third sub-gate signal to the third sub-gate line ; and a data driver configured to supply a data voltage to the data line. A length of a period in which the third sub-gate signal is supplied during a display scan period is different from a length of a period in which the third sub-gate signal is supplied during a self-scan period. The third sub-gate signal is provided to control a time at which an electrode of the light-emitting element is initialized. According to some embodiments, the sub-pixel is further connected to a first sub-light emission control line and a second sub-light emission control line. The sub-pixel may include a first transistor to control driving current, a second transistor connected between the data line and a third node and including a gate electrode connected to the first sub-gate line , a sixth transistor connected between a second node and a fourth node and including a gate electrode connected to the second sub-light emission control line , and a fourth transistor connected between a node providing an initialization voltage and the fourth node, and including a gate electrode connected to the third sub-gate line. The light-emitting element may be connected between the fourth node and a node which receives a second power supply voltage. The gate driver may be further configured to supply a first sub-light emission control signal to the first sub-light emission control line and a second sub-light emission control signal to the second sub-light emission control line. This feature defines a specific and operable pixel circuit structure, providing a concrete hardware implementation that is capable of performing the required initialization, data writing, and emission control functions. According to some embodiments, the data voltage may be written to the sub-pixel during the display scan period, and the data voltage may not be written to the sub-pixel during the self-scan period. This feature enables low-power operation at variable refresh rates by allowing the display to re-render a static image from memory without the power consumption associated with driving the data lines again. According to some embodiments, during the display scan period, the gate driver may supply the third sub-gate signal for a first period, and during the self-scan period, the gate driver may supply the third sub-gate signal for a second period. By formally defining the "first period" and "second period", this claim provides a clear structure and antecedent basis that enables the subsequent claims to define specific, optimized initialization timing schemes. In an embodiment, a length of the first period may be longer than a length of the second period. This specific timing scheme (longer initialization during display scan) ensures a more thorough and stable initialization of the pixel electrode during the complex display scan operation, which is critical for preventing image artifacts. A length between an end time of a non-emission period including the first period and an end time of the first period may be the same as a length between an end time of a non-emission period in