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EP-4738336-A2 - PIXEL CIRCUIT, DISPLAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY DEVICE

EP4738336A2EP 4738336 A2EP4738336 A2EP 4738336A2EP-4738336-A2

Abstract

A pixel circuit (100), a display substrate (601), a display panel (600, 701), and a display device (700). The pixel circuit (100) comprises: a first driving circuit (101), a second driving circuit (111), a first light emitting control circuit, a second light emitting control circuit, a storage circuit (103), and a data writing circuit (104). The first light emitting control circuit is configured to control connection or disconnection between the first driving circuit (101) and a light emitting element and control connection or disconnection between the first driving circuit (101) and a first power line (VDD1); the second light emitting control circuit is configured to control connection or disconnection between the second driving circuit (111) and the light emitting element and control connection or disconnection between the second driving circuit (111) and a second power line (VDD2); the data writing circuit (104) is configured to write a data voltage into the first driving circuit (101); the first driving circuit (101) and the second driving circuit (111) are configured to control, on the basis of the same data voltage, a driving current driving the light emitting element to emit light; the storage circuit (103) is configured to maintain voltages of a control end of the first driving circuit (101) and a control end of the second driving circuit (111).

Inventors

  • GU, Pinchao
  • HUANG, WEIYUN
  • CHENG, Yudiao
  • WU, CHAO

Assignees

  • Boe Technology Group Co., Ltd.
  • Chengdu BOE Optoelectronics Technology Co., Ltd.

Dates

Publication Date
20260506
Application Date
20210517

Claims (15)

  1. A display substrate (601), comprising a base substrate (300) and a plurality of sub-pixels arranged on the base substrate (300), wherein each of the plurality of sub-pixels comprises a pixel circuit (100) and a light-emitting element (200), the pixel circuit (100) comprises: a first driving circuit (101), a second driving circuit (111), a first light-emitting control circuit (102), a second light-emitting control circuit (112), a storage circuit (103), and a data writing circuit (104), the first light-emitting control circuit (102) is electrically connected to a first power line (VDD1), the first driving circuit (101), and the light-emitting element (200), and is configured to control a connection between the first driving circuit (101) and the light-emitting element (200) to be turned on or off and to control a connection between the first driving circuit (101) and the first power line (VDD1) to be turned on or off; the second light-emitting control circuit (112) is electrically connected to a second power line (VDD2), the second driving circuit (111), and the light-emitting element (200), and is configured to control a connection between the second driving circuit (111) and the light-emitting element (200) to be turned on or off and to control a connection between the second driving circuit (111) and the second power line (VDD2) to be turned on or off; the data writing circuit (104) is electrically connected to the first driving circuit (101), and is configured to write a data voltage into the first driving circuit (101); the first driving circuit (101) and the second driving circuit (111) are configured to control a driving current for driving the light-emitting element (200) to emit light based on a same data voltage; and the storage circuit (103) is electrically connected to a control terminal of the first driving circuit (101) and a control terminal of the second driving circuit (111), and is configured to maintain a voltage of the control terminal of the first driving circuit (101) and a voltage of the control terminal of the second driving circuit (111); the base substrate (300) comprises a first display region (10) and a second display region (20), the second display region (20) at least partially surrounds the first display region (10), the display substrate (601) has a first side for display and a second side opposite to the first side, and the first display region (10) allows light from the first side to be at least partially transmitted to the second side; the plurality of sub-pixels comprise a plurality of first sub-pixels (P1) and a plurality of second sub-pixels (P2); light-emitting elements (200) of the plurality of first sub-pixels (P1) are in the first display region (10), and pixel circuits (100) of the plurality of first sub-pixels (P1) are in the second display region (20); light-emitting elements (200) and pixel circuits (100) of the plurality of second sub-pixels (P2) are in the second display region (20); and the display substrate (601) further comprises a plurality of data lines (Vd) connected with pixel circuits (100) of the plurality of first sub-pixels (P1), and each of the plurality of data lines (Vd) connected with the pixel circuits (100) of the plurality of first sub-pixels (P1) at least partially passes through the first display region (10) and then extends to the second display region (20).
  2. The display substrate (601) according to claim 1, wherein the display substrate (601) further comprises a plurality of data lines (Vd) connected with pixel circuits (100) of the plurality of second sub-pixels (P2), and each of the plurality of data lines (Vd) connected with the pixel circuits (100) of the plurality of second sub-pixels (P2) extends in the second display region (20).
  3. The display substrate (601) according to claim 1, wherein a pixel circuit (100) of a first sub-pixel (P1) of the plurality of first sub-pixels (P1) is connected to a light-emitting element (200) of the first sub-pixel (P1) through a connection line (VDDc), and the connection line (VDDc) extends from the pixel circuit (100) of the first sub-pixel (P1) in the second display region (20) to the light-emitting element (200) of the first sub-pixel (P1) in the first display region (10).
  4. The display substrate (601) according to claim 1, wherein the pixel circuit (100) further comprises a power connection line (VDDc), wherein the first power line (VDD1) and the second power line (VDD2) are electrically connected to each other through the power connection line (VDDc).
  5. The display substrate (601) according to claim 4, wherein the pixel circuit (100) has a first functional layer (540) and a second functional layer (530), the first functional layer (540) and the second functional layer (530) are on the base substrate (300), and the first functional layer (540) is on a side of the second functional layer (530) away from the base substrate (300) in a direction perpendicular to the base substrate (300); the first power line (VDD1) and the second power line (VDD2) are in the first functional layer (540); the power connection line (VDDc) is in the second functional layer (530); and the power connection line (VDDc) is electrically connected to the first power line (VDD1) and the second power line (VDD2) through holes.
  6. The display substrate (601) according to claim 1, wherein the control terminal of the first driving circuit (101) and the control terminal of the second driving circuit (111) are electrically connected, the pixel circuit (100) further comprises a first gate connection line (Gc1), a second gate connection line (Gc2), and a third gate connection line (Gc3); the control terminal of the first driving circuit (101) and the control terminal of the second driving circuit (111) are electrically connected through the first gate connection line (Gc1), the second gate connection line (Gc2), and the third gate connection line (Gc3); the control terminal of the first driving circuit (101) is electrically connected to the first gate connection line (Gc1), and the control terminal of the second driving circuit (111) is electrically connected to the second gate connection line (Gc2); and the third gate connection line (Gc3) is used to electrically connect the first gate connection line (Gc1) and the second gate connection line (Gc2) to electrically connect the control terminal of the first driving circuit (101) to the control terminal of the second driving circuit (111).
  7. The display substrate (601) according to claim 6, wherein the pixel circuit (100) has a first functional layer (540) and a second functional layer (530), the first functional layer (540) and the second functional layer (530) are on the base substrate (300), and the first functional layer (540) is on a side of the second functional layer (530) away from the base substrate (300) in a direction perpendicular to the base substrate (300); the first gate connection line (Gc1) and the second gate connection line (Gc2) are in the first functional layer (540); the third gate connection line (Gc3) is in the second functional layer (530); and the third gate connection line (Gc3) is connected to the first gate connection line (Gc1) and the second gate connection line (Gc2) through holes.
  8. The display substrate (601) according to claim 6, wherein the first driving circuit (101) comprises a first driving transistor (T11), and the second driving circuit (111) comprises a second driving transistor (T12), the control terminal of the first driving circuit (101) comprises a gate electrode of the first driving transistor (T11), the control terminal of the second driving circuit (111) comprises a gate electrode of the second driving transistor (T12), a threshold voltage of the first driving transistor (T11) is identical to a threshold voltage of the second driving transistor (T12).
  9. The display substrate (601) according to claim 1, wherein the pixel circuit (100) further comprises a threshold compensation circuit (105), the threshold compensation circuit (105) is electrically connected to the control terminal of the first driving circuit (101) and the control terminal of the second driving circuit (111), and is configured to perform threshold compensation on the first driving circuit (101).
  10. The display substrate (601) according to claim 1, wherein the pixel circuit (100) further comprises a first initialization circuit (106) and a second initialization circuit (107), the first initialization circuit (106) is electrically connected to the control terminal of the first driving circuit (101) and the control terminal of the second driving circuit (111), and is configured to initialize the control terminal of the first driving circuit (101) and the control terminal of the second driving circuit (111); and the second initialization circuit (107) is electrically connected to a first electrode of the light-emitting element (200) and is configured to initialize the first electrode of the light-emitting element (200).
  11. The display substrate (601) according to claim 1, wherein the first light-emitting control circuit (102) comprises a first light-emitting control sub-circuit (1021) and a second light-emitting control sub-circuit (1022); the first light-emitting control sub-circuit (1021) is connected to a first terminal of the first driving circuit (101) and the first power line (VDD1), and is configured to turn on or off a connection between the first terminal of the first driving circuit (101) and the first power line (VDD1); and the second light-emitting control sub-circuit (1022) is electrically connected to a second terminal of the first driving circuit (101) and a first electrode of the light-emitting element (200), and is configured to turn on or off a connection between the second terminal of the first driving circuit (101) and the first electrode of the light-emitting element (200); wherein the second light-emitting control circuit (112) comprises a third light-emitting control sub-circuit (1121) and a fourth light-emitting control sub-circuit (1122), the third light-emitting control sub-circuit (1121) is connected to a first terminal of the second driving circuit (111) and the second power line (VDD2), and is configured to turn on or off a connection between the first terminal of the second driving circuit (111) and the second power line (VDD2), the fourth light-emitting control sub-circuit (1122) is electrically connected to a second terminal of the second driving circuit (111) and a first electrode of the light-emitting element (200), and is configured to turn on or off a connection between the second terminal of the second driving circuit (111) and the first electrode of the light-emitting element (200).
  12. The display substrate (601) according to claim 1, wherein the pixel circuit (100) further comprises a threshold compensation circuit (105), a first initialization circuit (106), and a second initialization circuit (107), the first light-emitting control circuit (102) comprises a first light-emitting control sub-circuit (1021) and a second light-emitting control sub-circuit (1022), and the second light-emitting control circuit (112) comprises a third light-emitting control sub-circuit (1121) and a fourth light-emitting control sub-circuit (1122); the first driving circuit (101) comprises a first driving transistor (T11), the second driving circuit (111) comprises a second driving transistor (T12), the first light-emitting control sub-circuit (1021) comprises a first light-emitting control transistor (T21), the second light-emitting control sub-circuit (1022) comprises a second light-emitting control transistor (T31), the third light-emitting control sub-circuit (1121) comprises a third light-emitting control transistor (T22), the fourth light-emitting control sub-circuit (1122) comprises a fourth light-emitting control transistor (T32), the data writing circuit (104) comprises a data writing transistor (T4), the storage circuit (103) comprises a storage capacitor (C), the threshold compensation circuit (105) comprises a threshold compensation transistor (T5), the first initialization circuit (106) comprises a first initialization transistor (T6), and the second initialization circuit (107) comprises a second initialization transistor (T7); the control terminal of the first driving circuit (101) comprises a gate electrode of the first driving transistor (T11), the control terminal of the second driving circuit (111) comprises a gate electrode of the second driving transistor (T12); a first electrode of the data writing transistor (T4) is electrically connected to a data line (Vd) to receive the data voltage, a second electrode of the data writing transistor (T4) is electrically connected to a first electrode of the first driving transistor (T11), and a gate electrode of the data writing transistor (T4) is electrically connected to a first scan line(G1); a first electrode of the first light-emitting control transistor (T21) is electrically connected to the first power line (VDD1), a second electrode of the first light-emitting control transistor (T21) is electrically connected to the first electrode of the first driving transistor (T11), and a gate electrode of the first light-emitting control transistor (T21) is electrically connected to a first light-emitting control signal line (EM1); a first electrode of the second light-emitting control transistor (T31) is electrically connected to a second electrode of the first driving transistor (T11), a second electrode of the second light-emitting control transistor (T31) is electrically connected to a first electrode of the light-emitting element (200), and a gate electrode of the second light-emitting control transistor (T31) is electrically connected to a second light-emitting control signal line(EM2); a first electrode of the third light-emitting control transistor (T22) is electrically connected to the second power line (VDD2), a second electrode of the third light-emitting control transistor (T22) is electrically connected to a first electrode of the second driving transistor (T12), and a gate electrode of the third light-emitting control transistor (T22) is electrically connected to a third light-emitting control signal line (EM3); a first electrode of the fourth light-emitting control transistor (T32) is electrically connected to a second electrode of the second driving transistor (T12), a second electrode of the fourth light-emitting control transistor (T32) is electrically connected to the first electrode of the light-emitting element (200), and a gate electrode of the fourth light-emitting control transistor (T32) is electrically connected to a fourth light-emitting control signal line (EM4); a first electrode of the threshold compensation transistor (T5) is electrically connected to the second electrode of the first driving transistor (T11), a second electrode of the threshold compensation transistor (T5) is electrically connected to the gate electrode of the first driving transistor (T11) and the gate electrode of the second driving transistor (T12), and a gate electrode of the threshold compensation transistor (T5) is electrically connected to a second scan line (G2); a first electrode of the first initialization transistor (T6) is electrically connected to a first initialization voltage line (Vinit1), a second electrode of the first initialization transistor (T6) is electrically connected to the gate electrode of the first driving transistor (T11) and the gate electrode of the second driving transistor (T12), and a gate electrode of the first initialization transistor (T6) is electrically connected to a first initialization control signal line (Rst1); a first electrode of the second initialization transistor (T7) is electrically connected to a second initialization voltage line (Vinit2), a second electrode of the second initialization transistor (T7) is electrically connected to the first electrode of the light-emitting element (200), and a gate electrode of the second initialization transistor (T7) is electrically connected to a second initialization control signal line (Rst2); and a first electrode of the storage capacitor (C) is electrically connected to the gate electrode of the first driving transistor (T11) and the gate electrode of the second driving transistor (T12), and a second electrode of the storage capacitor (C) is electrically connected to the first power line (VDD1); preferably, the pixel circuit (100) has a first functional layer (540), a second functional layer (530), and a third functional layer (520), the first functional layer (540), the second functional layer (530), and the third functional layer (520) are on the base substrate (300), and in a direction perpendicular to the base substrate (300), the second functional layer (530) is between the first functional layer (540) and the third functional layer (520), the second functional layer (530) is on a side of the third functional layer (520) away from the base substrate (300), the first functional layer (540) is on a side of the second functional layer (530) away from the base substrate (300), the first scan line(G1), the second scan line (G2), the first light-emitting control signal line (EM1), the second light-emitting control signal line(EM2), the third light-emitting control signal line (EM3), and the fourth light-emitting control signal line (EM4) are in the third functional layer (520); the data line, the first power line (VDD1), and the second power line (VDD2) are in the first functional layer (540); and the first initialization voltage line (Vinit1) and the second initialization voltage line (Vinit2) are in the second functional layer (530).
  13. The display substrate (601) according to claim 12, wherein the first driving transistor (T11) and the second driving transistor (T12) transmit the driving current to the light-emitting element (200) to drive the light-emitting element (200) to emit light in a light-emitting phase, the driving current is expressed as: I OLED = K 1 ∗ Vgs 1 − Vth 1 + K 2 ∗ Vgs 2 − Vth 2 , where I OLED represents the driving current, K1 is a process constant of the first driving transistor (T11), Vgs1 is a voltage difference between the gate electrode and the first electrode of the first driving transistor (T11) in the light-emitting phase, Vth1 is a threshold voltage of the first driving transistor (T11), K2 is a process constant of the second driving transistor (T12), Vgs2 is a voltage difference between the gate electrode and the first electrode of the second driving transistor (T12) in the light-emitting stage, and Vth2 is a threshold voltage of the second driving transistor (T12).
  14. The display substrate (601) according to claim 1, wherein the first display region (10) comprises a plurality of pixel regions (PD), each pixel region (PD) of the plurality of pixel regions (PD) comprises a first sub-region (PD1) and a second sub-region (PD2) that do not overlap each other, the first driving circuit (101), the first light-emitting control circuit (102), the storage circuit (103), and the data writing circuit (104) in the pixel circuit (100) are in a first sub-region (PD1) of a corresponding pixel region (PD), the second driving circuit (111) and the second light-emitting control circuit (112) in the pixel circuit (100) are in a second sub-region (PD2) of the corresponding pixel region; the pixel circuits (100) of the plurality of first sub-pixels (P1) and the pixel circuits (100) of the plurality of second sub-pixels (P2) are in one-to-one correspondence with the plurality of pixel regions (PD); preferably, the first sub-region (PD1) of each pixel region (PD) comprises a first side and a second side opposite to each other, the pixel circuits (100) of the plurality of first sub-pixels (P1) constitute a plurality of first repeating units (RP1), each first repeating unit (RP1) comprises pixel circuits (100) of four first sub-pixels (P1) arranged in two rows and two columns, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four first sub-pixels (P1), of a first sub-pixel (P1) located in a first row and a first column is on a first side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the first sub-pixel (P1) located in the first row and the first column, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit (100), among the pixel circuits (100) of the four first sub-pixels (P1), of a first sub-pixel (P1) located in a second row and the first column is on a first side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the first sub-pixel (P1) located in the second row and the first column, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four first sub-pixels (P1), of a first sub-pixel (P1) located in the first row and a second column is on a second side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the first sub-pixel (P1) located in the first row and the second column, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four first sub-pixels (P1), of a first sub-pixel (P1) located in the second row and the second column is on a second side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the first sub-pixel (P1) located in the second row and the second column, the pixel circuits (100) of the plurality of second sub-pixels (P2) constitute a plurality of second repeating units (RP2), each second repeating unit (RP2) comprises pixel circuits (100) of four second sub-pixels (P2) arranged in two rows and two columns, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four second sub-pixels (P2), of a second sub-pixel located in a first row and a first column is on a second side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the second sub-pixel located in the first row and the first column, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four second sub-pixels (P2), of a second sub-pixel located in a second row and the first column is on a second side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the second sub-pixel located in the second row and the first column, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four second sub-pixels (P2), of a second sub-pixel located in the first row and a second column is on a first side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the second sub-pixel located in the first row and the second column, a second sub-region (PD2) in a pixel region (PD) corresponding to a pixel circuit, among the pixel circuits (100) of the four second sub-pixels (P2), of a second sub-pixel located in the second row and the second column is on a first side of a first sub-region (PD1) in the pixel region (PD) corresponding to the pixel circuit (100) of the second sub-pixel located in the second row and the second column; preferably, the plurality of first repeating units (RP1) and the plurality of second repeating units (RP2) constitute a plurality of repeating unit groups, and each repeating unit group in the plurality of repeating unit groups comprises two first repeating units (RP1) and two second repeating units (RP2), the two first repeating units (RP1) and the two second repeating units (RP2) are arranged in two rows and two columns, the two first repeating units (RP1) are respectively in a first row and a second column, and a second row and a first column, and the two second repeating units (RP2) are respectively in the first row and the first column, and the second row and the second column; or, the two first repeating units (RP1) are respectively in a first row and a first column, and a second row and a second column, and the two second repeating units (RP2) are respectively in the first row and the second column, and the second row and the first column; or, the first sub-pixel (P1) located in the first row and the first column among the four first sub-pixels (P1) and the second sub-pixel located in the first row and the first column among the four second sub-pixels (P2) are red sub-pixels, the first sub-pixel (P1) located in the second row and the first column among the four first sub-pixels (P1) and the second sub-pixel located in the second row and the first column among the four second sub-pixels (P2) are blue sub-pixels, the first sub-pixel (P1) located in the first row and the second column among the four first sub-pixels (P1), the first sub-pixel (P1) located in the second row and the second column among the four first sub-pixels (P1), the second sub-pixel located in the first row and the second column among the four second sub-pixels (P2), and the second sub-pixel located in the second row and the second column among the four second sub-pixels (P2) are green sub-pixels.
  15. A display panel (600, 701), comprising the display substrate (601) according to any one of claims 1-14.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority of Chinese Patent Application No. 202010606662.9, filed on June 29, 2020, and the entire content disclosed by the Chinese patent application is incorporated herein by reference as part of the present application for all purposes. TECHNICAL FIELD The embodiments of the present disclosure relate to a pixel circuit, a display substrate, a display panel, and a display device. BACKGROUND With the in-depth development of full-screen display, it has developed from a scheme of placing a camera in an opening region of a display panel to a scheme of combining the camera with the display panel, that is, the scheme of "under-screen camera ". For the display design of "under-screen camera", a region, where the camera is placed, of the display panel is a low PPI (Pixels Per Inch) region, so that the transmittance of the low PPI region can meet the requirements of camera imaging. However, because the PPI of the pixel arrangement in the low PPI region is lower than the PPI of a normal display region, the display brightness of the low PPI region is lower than the display brightness of the normal display region. SUMMARY At least one embodiment of the present disclosure provides a pixel circuit, comprising: a first driving circuit, a second driving circuit, a first light-emitting control circuit, a second light-emitting control circuit, a storage circuit, and a data writing circuit. The first light-emitting control circuit is electrically connected to a first power line, the first driving circuit, and a light-emitting element, and is configured to control a connection between the first driving circuit and the light-emitting element to be turned on or off and to control a connection between the first driving circuit and the first power line to be turned on or off; the second light-emitting control circuit is electrically connected to a second power line, the second driving circuit, and the light-emitting element, and is configured to control a connection between the second driving circuit and the light-emitting element to be turned on or off and to control a connection between the second driving circuit and the second power line to be turned on or off; the data writing circuit is electrically connected to the first driving circuit, and is configured to write a data voltage into the first driving circuit; the first driving circuit and the second driving circuit are configured to control a driving current for driving the light-emitting element to emit light based on a same data voltage; and the storage circuit is electrically connected to a control terminal of the first driving circuit and a control terminal of the second driving circuit, and is configured to maintain a voltage of the control terminal of the first driving circuit and a voltage of the control terminal of the second driving circuit. For example, the pixel circuit provided by at least one embodiment of the present disclosure further includes a power connection line, the first power line and the second power line are electrically connected to each other through the power connection line. For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the pixel circuit is on a base substrate, the pixel circuit has a first functional layer and a second functional layer, the first functional layer and the second functional layer are on the base substrate, and the first functional layer is on a side of the second functional layer away from the base substrate in a direction perpendicular to the base substrate; the first power line and the second power line are in the first functional layer; the power connection line is in the second functional layer; and the power connection line is electrically connected to the first power line and the second power line through holes. For example, in the pixel circuit provided by at least one embodiment of the present disclosure, the control terminal of the first driving circuit and the control terminal of the second driving circuit are electrically connected. For example, the pixel circuit provided by at least one embodiment of the present disclosure further comprises a first gate connection line, a second gate connection line, and a third gate connection line; the control terminal of the first driving circuit and the control terminal of the second driving circuit are electrically connected through the first gate connection line, the second gate connection line, and the third gate connection line; the control terminal of the first driving circuit is electrically connected to the first gate connection line, and the control terminal of the second driving circuit is electrically connected to the second gate connection line; and the third gate connection line is used to electrically connect the first gate connection line and the second gate connection line to electrically connect the control terminal of the first driving circuit