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EP-4738357-A1 - PRE-PATTERNED ADHESIVE TAPE FOR ENABLING DOUBLE-SIDED CIRCUIT ASSEMBLY

EP4738357A1EP 4738357 A1EP4738357 A1EP 4738357A1EP-4738357-A1

Abstract

A method of producing a circuit die where the method includes applying a pre-patterned backing tape to a first surface of a semiconductor substrate that includes the first surface and a second surface, the second surface including one or more circuits; coating the second surface with an encapsulant; removing a patterned portion of the pre-patterned backing tape to expose one or more contact pads on the first surface; applying one of an electrically conductive adhesive (ECA) or solder to the one or more contact pads on the first surface; and coupling an electrical component to the contact pads using the ECA or solder.

Inventors

  • KANTH, NAMRATA
  • Hayes, Scott M
  • HOOPER, STEPHEN RYAN
  • SHADE, Douglas Michael

Assignees

  • NXP USA, Inc.

Dates

Publication Date
20260506
Application Date
20251024

Claims (15)

  1. A method of producing a circuit die, the method comprising: applying a pre-patterned backing tape to a first surface of a semiconductor substrate that includes the first surface and a second surface, the second surface including one or more circuits; coating the second surface with an encapsulant; removing a patterned portion of the pre-patterned backing tape to expose one or more contact pads on the first surface; applying one of an electrically conductive adhesive (ECA) or solder to the one or more contact pads on the first surface; and coupling an electrical component to the contact pads using the ECA or solder.
  2. The method of claim 1, wherein, before applying the pre-patterned backing tape, the method further comprising selecting the pre-patterned backing tape.
  3. The method of claim 1 or claim 2, further comprising coating the first surface with a second encapsulant.
  4. The method of claim 3, wherein the second protective material comprises a conformal coating.
  5. The method of claim 3, wherein the second protective material comprises an encapsulant.
  6. The method according to any preceding claim, wherein the pre-patterned backing tape is non-conductive.
  7. The method according to any preceding claim, during the coating of the second surface, the method comprises preventing resin bleed by the pre-patterned backing tape.
  8. The method according to any preceding claim, wherein the electrical component comprises a battery.
  9. The method according to any preceding claim, wherein the electrical component comprises one or more of a resistor, an inductor, or a capacitor.
  10. The method according to any preceding claim, wherein during the applying the one of the ECA or the solder, preventing, by a remaining portion of the pre-patterned backing tape, the ECA or the solder from contacting adjacent contact pads.
  11. The method according to any preceding claim, wherein the semiconductor substrate comprises one of a lead frame package, a fan-out wafer-level scale chip package, a flip-chip package, or a mold-array process ball grid array package.
  12. A device comprising: a circuit package including a semiconductor substrate including an active surface and a second surface, the semiconductor substrate including a circuit coupled to one or more contact pads of an active surface of the semiconductor substrate and including an encapsulant material disposed on the active surface and at least partially over the circuit; a patterned backing tape coupled to the second surface of the semiconductor substrate, the patterned backing tape including a remaining portion including openings corresponding to a pattern of a removed patterned portion, the openings at least partially aligned with one or more contact pads on the second surface of the semiconductor substrate; and a circuit component coupled to the one or more contact pads on the second surface of the semiconductor substrate.
  13. The device of claim 12, wherein the circuit component comprises at least one of a battery, one or more of a resistor, a capacitor, or an inductor.
  14. The device of claim 12 or claim 13, further comprising one of an electrically conductive adhesive or a solder on the one or more contact pads to electrically and mechanically couple the circuit component to the one or more contact pads.
  15. The device according to any of claim 12 to claim 14, further comprising a second encapsulant material disposed on the second surface of the semiconductor substrate and optionally over the circuit component.

Description

FIELD OF USE The present disclosure generally relates to semiconductor circuits, and more particularly to double-sided circuits including a patterned adhesive tape and methods of assembly using pre-patterned adhesive tape. BACKGROUND Adhesive tape with high thermal and electrical insulation properties, such as Kapton® tape produced by Dupont Electronics, Inc. of Delaware, is often used during microelectronic package assembly, for example, as a solder mask or heat protector, to mask areas during painting or plating, to splice together flexible printed circuit boards, or for packaging semiconductors. BRIEF DESCRIPTION OF THE DRAWINGS The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures and in the detailed description indicates similar or identical items or features. FIG. 1A depicts a cross-sectional view of a portion of a microelectronic package array including a lead frame with one or more circuits and with pre-patterned backing tape, in accordance with one or more embodiments.FIG. 1B depicts a top view of the portion of the microelectronic package array of FIG. 1A including the pre-patterned backing tape and showing a first portion that remains on the substrate and a second portion that is removable according to the pattern, in accordance with one or more embodiments.FIG. 2 depicts a first portion of a method of producing a circuit die including producing microelectronic package array including a lead frame with exposed bond pads for attaching a battery or circuit components, in accordance with one or more embodiments.FIG. 3 depicts a second portion of the method of producing the circuit die including applying conductive material to the exposed bond pads, attaching a device, applying a coating, and singulating a microelectronic package from the microelectronic package array, in accordance with one or more embodiments.FIG. 4A depicts a cross-sectional view of the circuit of FIG. 3 including a conformal coating, in accordance with one or more embodiments.FIG. 4B depicts a cross-sectional view of the circuit of FIG. 3 including an encapsulant, in accordance with one or more embodiments.FIG. 5A depicts an embodiment of the circuit of FIG. 3 implemented as a fan-out wafer-level chip scale package (FO-WLCSP), in accordance with one or more embodiments.FIG. 5B depicts an embodiment of the circuit of FIG. 3 implemented as a flip-chip package, in accordance with one or more embodiments.FIG. 5C depicts an embodiment of the circuit of FIG. 3 implemented as a mold-array process ball grid array (MAP BGA), in accordance with one or more embodiments.FIG. 6 depicts a flow diagram of a method of producing a circuit die using a pre-patterned adhesive tape, in accordance with one or more embodiments. While implementations are described in this disclosure by way of example, those skilled in the art will recognize that the implementations are not limited to the examples or figures described. Rather, the figures and detailed description thereto are not intended to limit implementations to the form disclosed, but instead the intention is to cover all modifications, equivalents, and alternatives falling within the scope as defined by the appended claims. The headings used in this disclosure are for organizational purposes only and are not meant to limit the scope of the description or the claims. As used throughout this application, the word "may" is used in a permissive sense (in other words, the term "may" is intended to mean "having the potential to") instead of in a mandatory sense (as in "must"). Similarly, the terms "include," "including," and "includes" mean "including, but not limited to." DETAILED DESCRIPTION In one or more embodiments, a method or process flow may begin with a processed microelectronic package array, which may have received back-grinding processing. As used herein, the term "microelectronic package array" refers to a semiconductor substrate with a first side upon which distinct active circuit areas are formed. Each distinct active circuit area may include an active circuit area, one or more conductive pads on a top surface, scribe-lane areas between the active circuit areas, and optionally a seal-ring structure. A dielectric material may be deposited conformally onto a top surface of each of the active circuit areas and on the sidewalls. Embodiments of circuits and methods are described below that utilize a backing tape, such as Kapton® tape produced by Dupont Electronics, Inc. of Delaware, to prevent resin bleed. The backing tape may be formed from polyimide-based or polyethylene-based material that remains stable across a wide-range of temperatures (such as from -269 degrees Celsius to +400 degrees Celsius) and that is electrically insulative. The backing tape may be coated with a silicone