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EP-4738358-A1 - OPTIMIZED SINGLE ENDED EPCM READ METHODOLOGY ADAPTIVE TO TEMPERATURE VARIATIONS

EP4738358A1EP 4738358 A1EP4738358 A1EP 4738358A1EP-4738358-A1

Abstract

Readout circuitry for embedded phase change memory (ePCM) cells is disclosed. The circuitry includes a temperature sensor that outputs a signal indicating whether the sensed temperature is above or below a threshold. A microcontroller generates read and trim signals, with the trim signal based on the temperature signal. A phase generation circuit receives these signals and generates precharge and evaluation signals based on the trim signal. A sense amplifier, controlled by the precharge and evaluation signals, compares the ePCM cell current to a reference current to generate an output. The circuitry dynamically adjusts its timing parameters in response to temperature changes, providing for reliable read operations across varying conditions.

Inventors

  • JAIN, ABHISHEK
  • JAIN, SHUBHAM

Assignees

  • STMicroelectronics International N.V.

Dates

Publication Date
20260506
Application Date
20251020

Claims (20)

  1. A readout circuit for an embedded phase change memory (ePCM) cell, comprising: a temperature sensor (14) configured to output a temperature signal (THS_OUT) indicative of whether a sensed temperature is above or below a threshold temperature; a microcontroller (13) configured to generate a read signal (READ) and a trim signal (TRIM), the trim signal (TRIM) being generated based upon the temperature signal (THS_OUT); a phase generation circuit (11') coupled to the microcontroller (13) and configured to receive the read signal (READ) and the trim signal (TRIM), and to generate a precharge signal (PRECH) and an evaluation signal (EVAL) based thereupon; and a sense amplifier (12') coupled to the phase generation circuit (11') to receive the precharge signal (PRECH) and the evaluation signal (EVAL), the sense amplifier (12') being configured to compare, under timing control of the precharge signal (PRECH) and the evaluation signal (EVAL), a cell current from the ePCM cell (15) to a reference current (IREF) and generate an output signal (DOUT) based on the comparison.
  2. The readout circuit of claim 1, wherein the phase generation circuit (11') is configured to set a duration of time between deassertion of the precharge signal (PRECH) and assertion of the evaluation signal (EVAL) based on the trim signal (TRIM).
  3. The redout circuit of claim 1, wherein the temperature sensor (14) is hysteretic to prevent rapid oscillations in the temperature signal (THS_OUT) due to small temperature fluctuations near the threshold temperature.
  4. The readout circuit of claim 1, wherein the microcontroller (13) is further configured to: set the trim signal (TRIM) to indicate insertion of a wait state based on the trim signal (TRIM), the wait state causing skipping of transition of the evaluation signal (EVAL) during a current read cycle.
  5. The readout circuit of claim 1, wherein the phase generation circuit (11') comprises: a first delay circuit configured to generate the precharge signal (PRECH); and a second delay circuit configured to generate the evaluation signal (EVAL).
  6. The readout circuit of claim 5, wherein the first delay circuit comprises: a first capacitor (C1); a first adjustable current source (41) coupled to the first capacitor (C1) and configured to discharge the first capacitor (C1); and a first set of inverters (21, 22, 23) coupled to the first capacitor (C1) and configured to generate the precharge signal (PRECH) based on a voltage across the first capacitor (C1).
  7. The readout circuit of claim 6, wherein the second delay circuit comprises: a second capacitor (C2); a second adjustable current source (42) coupled to the second capacitor (C2) and configured to discharge the second capacitor (C2); and a second set of inverters (30, 31, 32) coupled to the second capacitor (C2) and configured to generate the evaluation signal (EVAL) based on a voltage across the second capacitor (C2).
  8. The readout circuit of claim 10, wherein the first and second adjustable current sources (41, 42) are configured to be adjusted based on the trim signal (TRIM) received from the microcontroller (13).
  9. The readout circuit of claim 8, wherein adjusting the first and second adjustable current sources (41, 42) based on the trim signal (TRIM) controls the delay between the deassertion of the precharge signal (PRECH) and the assertion of the evaluation signal (EVAL).
  10. The readout circuit of claim 5, wherein the second delay circuit is triggered by a transition of the precharge signal (PRECH).
  11. The readout circuit of claim 5, wherein the phase generation circuit (11') further comprises: a first logic circuit coupled to the first delay circuit and configured to control the assertion and deassertion of the precharge signal (PRECH); and a second logic circuit coupled to the second delay circuit and configured to control the assertion and deassertion of the evaluation signal (EVAL).
  12. The readout circuit of claim 11, wherein the first logic circuit comprises: a first NOR gate (24) having inputs receiving the precharge signal (PRECH) and an output of a second NOR gate (28); a first NAND gate (25) having inputs receiving a stop read signal (STOP_READ) and a data output signal (DOUT); a third NOR gate (27) having inputs receiving an output of the first NAND gate (25) and the precharge signal (PRECH); and wherein the second NOR gate (28) has inputs receiving an output of the third NOR gate (27) and an output (PHASE1) of the first delay circuit.
  13. The readout circuit of claim 11, wherein the second logic circuit comprises: a second NAND gate (33) having inputs receiving an inverted precharge signal (PRECHn) and an output (PHASE2) of the second delay circuit; and an inverter (34) coupled to an output of the second NAND gate (33) and configured to generate the evaluation signal (EVAL).
  14. A readout circuit for a memory cell, comprising: a temperature sensor (14) configured to output a temperature signal (THS_OUT) indicative of a sensed temperature; a timing control circuit (11') coupled to the temperature sensor (14) and configured to: receive the temperature signal (THS_OUT); generate a precharge signal (PRECH) and an evaluation signal (EVAL) for reading the memory cell; and adjust a duration of time between deassertion of the precharge signal (PRECH) and assertion of the evaluation signal (EVAL) based on the temperature signal (THS_OUT); and a sense amplifier (12') coupled to the timing control circuit (11') to receive the precharge signal (PRECH) and the evaluation signal (EVAL), the sense amplifier (12') being configured to compare a cell current from the memory cell to a reference current (IREF) and generate an output signal (DOUT) based on the comparison, under timing control of the precharge signal (PRECH) and the evaluation signal (EVAL).
  15. The readout circuit of claim 14, wherein the timing control circuit (11') is configured to increase the duration of time between deassertion of the precharge signal (PRECH) and assertion of the evaluation signal (EVAL) when the sensed temperature is below a threshold temperature.
  16. The readout circuit of claim 14, wherein the temperature sensor (14) is hysteretic to prevent rapid oscillations in the temperature signal (THS_OUT) due to small temperature fluctuations near a threshold temperature.
  17. The readout circuit of claim 14, wherein the timing control circuit (11') is further configured to: insert a wait state based on the temperature signal (THS_OUT), the wait state causing skipping of transition of the evaluation signal (EVAL) during a current read cycle.
  18. A readout circuit for an embedded phase change memory (ePCM) cell, comprising: a microcontroller (13) configured to: latch a plurality of test addresses spanning the ePCM cell (15); perform both a slow read operation and a normal read operation at each of the plurality of test addresses; compare results of the slow read operation and the normal read operation at each test address; generate a temperature signal (THS_OUT) based on whether the slow read operation matches the normal read operation at each test address; and generate a trim signal (TRIM) based upon the temperature signal (THS_OUT); a phase generation circuit (11') coupled to the microcontroller (13) and configured to receive the read signal (READ) and the trim signal (TRIM), and to generate a precharge signal (PRECH) and an evaluation signal (EVAL) based thereupon; and a sense amplifier (12') coupled to the phase generation circuit (11') to receive the precharge signal (PRECH) and the evaluation signal (EVAL), the sense amplifier (12') being configured to compare a cell current from the ePCM cell (15) to a reference current (IREF) and generate an output signal (DOUT) based on the comparison, under timing control of the precharge signal (PRECH) and the evaluation signal (EVAL).
  19. The readout circuit of claim 18, wherein the plurality of test addresses comprises: a lower address in the ePCM cell; a higher address in the ePCM cell; and an intermediate address between the lower address and the higher address.
  20. The readout circuit of claim 18, wherein the microcontroller (13) is configured to: set the temperature signal (THS_OUT) to a first value when the slow read operation matches the normal read operation at all test addresses; and set the temperature signal (THS_OUT) to a second value when the slow read operation differs from the normal read operation at any test address.

Description

TECHNICAL FIELD This disclosure relates to the field of embedded Phase Change Memory (ePCM) devices. Specifically, it addresses improvements in read operations for ePCM cells across varying temperature conditions through improved readout circuitry. BACKGROUND Embedded Phase Change Memory (ePCM) is a type of non-volatile memory that has gained attention in recent years due to its potential for high-density storage and fast read/write operations. In ePCM devices, information is stored by changing the physical state of a chalcogenide material between amorphous (high resistance) and crystalline (low resistance) states. The read operation for a given ePCM cell typically relies on a comparison of the current flowing through the ePCM cell (ICELL) with a reference current (IREF). This comparison allows the system to determine the logical state of the cell. The cell current ICELL is generated by applying a small read voltage across the ePCM cell and measuring the resulting current. The magnitude of the cell current ICELL depends on the resistance state of the cell, which corresponds to the stored data bit (0 or 1). A sample readout circuit 10 for an ePCM cell is shown in FIG. 1. The circuit includes a sense amplifier 12 that receives the cell current ICELL from the ePCM cell along with the reference current IREF. The reference current IREF is typically generated by a separate reference circuit and is set to a value between the expected currents for the low and high resistance states of the ePCM cell. The sense amplifier 12 is controlled by a precharge signal PRECH and an evaluation signal EVAL, which are generated by the phase generation circuitry 11. The phase generation circuitry 11 produces the PRECH and EVAL signals in response to the assertion of a read signal READ, indicating that the ePCM cell is to be read. During the read operation, the sense amplifier 12 compares the current ICELL to the current IREF. If the current ICELL is greater than the current IREF, it indicates that the ePCM cell is in a low resistance state (crystalline), typically representing a logical '1'. Conversely, if the current ICELL is less than the current IREF, it suggests the cell is in a high resistance state (amorphous), usually representing a logical '0'. The result of this comparison is then output as a data output signal DOUT, providing the logical value stored in the ePCM cell. FIG. 2 illustrates the timing diagram of a typical read operation. At time T1, after the rising edge of a clock signal CLK (which occurs prior to time T1), the READ signal is asserted, and the address ADDR0 of the cell to be read becomes valid. The precharge signal PRECH is then asserted by the phase generation circuitry 11 to begin precharging the sense amplifier 12, and the negated evaluation signal EVALN is deasserted (active low). The precharge operation continues for a duration TPRECH of the precharge signal PRECH, ending at time T2. During this time, the sense amplifier is prepared for the subsequent evaluation phase. There is a brief delay TD before the evaluation phase begins at time T3. At this point, the negated evaluation signal EVALN is asserted (active low, thus corresponding to active high assertion of the evaluation signal EVAL), initiating the comparison between the currents ICELL and IREF. The evaluation phase lasts for a duration TEVAL, which ends at time T4. During this duration, the sense amplifier 12 compares the current ICELL to the current IREF to determine the logical state of the ePCM cell. Near the end of this phase, the data output signal DATA_OUT becomes valid, representing the result of the comparison. At time T5, the stop read signal STOP_READ is asserted, indicating the completion of the read operation. Shortly after, the system prepares for the next read operation, with the address changing to ADDR1 for the subsequent read cycle having been loaded at time T4. In ePCM devices, accurate reading of cell states requires a minimum current window of typically 1 µA between the array cell current and the reference current. This current window is needed for the sense amplifier to reliably distinguish between the set (low resistance) and reset (high resistance) states of the memory cell. However, maintaining consistent read operations across a wide temperature range presents a significant challenge in ePCM technology. As illustrated in FIG. 3, the cell current ICELL in ePCM devices is not constant with respect to temperature. Instead, it exhibits a positive temperature coefficient, increasing as temperature rises. This temperature-dependent behavior creates several issues that complicate the read process. Firstly, there is the problem of current window reduction. This is explained in the context of the cell current ICELL, the set cell current, and the reset cell current - ICELL represents the current flowing through the ePCM cell during a read operation, and its value depends on whether the cell is in a set or reset state. The set cell