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EP-4738359-A1 - STATIC RANDOM ACCESS MEMORY DEVICE WITH PRE-CHARGE CIRCUIT SHARED BETWEEN DATA LINES AND BIT LINES

EP4738359A1EP 4738359 A1EP4738359 A1EP 4738359A1EP-4738359-A1

Abstract

A memory device (100) includes a first static random access memory array (102), a first multiplexer circuit (110), and a pre-charge circuit (112). The first static random access memory array (102) includes a plurality of first static random access memory cells (106_0, 108_0, 106_N, 108_N) coupled to a plurality of first complementary bit line pairs (BL[0], BLB[0], BL[1], BLB[1]), respectively. The first multiplexer circuit (110) is coupled between the first complementary bit line pairs (BL[0], BLB[0], BL[1], BLB[1]) and a complementary data line pair (DL, DLB). The pre-charge circuit (112) is configured to pre-charge the complementary data line pair (DL, DLB), and is further configured to pre-charge at least one of the first complementary bit line pairs (BL[0], BLB[0], BL[1], BLB[1]) through the first multiplexer circuit (110).

Inventors

  • YANG, TZU-HSIEN
  • CHIU, YI-TE

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260506
Application Date
20251014

Claims (15)

  1. A memory device (100, 320, 400) characterized by : a first static random access memory, SRAM, array (102, 304), comprising a plurality of first SRAM cells (106_0, 108_0, 106_N, 108_N) coupled to a plurality of first complementary bit line, BL, pairs (BL[0], BLB[0], BL[1], BLB[1]), respectively; a first multiplexer circuit (110, 322), coupled between the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) and a complementary data line, DL, pair (DL, DLB); and a pre-charge circuit (112, 326, 600), configured to pre-charge the complementary DL pair (DL, DLB), and further configured to pre-charge at least one of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) through the first multiplexer circuit (112, 326, 600).
  2. The memory device (100, 320, 400) of claim 1, characterized in that during a period of a pre-charge mode of the first SRAM array (102, 304), the first multiplexer circuit (112, 326, 600) connects each of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) to the complementary DL pair (DL, DLB).
  3. The memory device (320) of claim 1, characterized in that the memory device (320) further comprises: a second SRAM array (306), comprising a plurality of second SRAM cells coupled to a plurality of second complementary BL pairs, respectively; and a second multiplexer circuit (324), coupled between the plurality of second complementary BL pairs and the complementary DL pair; wherein the pre-charge circuit (326) is further configured to pre-charge at least one of the plurality of second complementary BL pairs through the second multiplexer circuit (324).
  4. The memory device (320) of claim 3, characterized in that during a period of a pre-charge mode of the first SRAM array (304), the first multiplexer circuit (322) is configured to connect the at least one of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) to the complementary DL pair (DL, DLB); and during a period of a pre-charge mode of the second SRAM array (306) that does not overlap the period of the pre-charge mode of the first SRAM array (304), the second multiplexer circuit (324) is configured to connect the at least one of the plurality of second complementary BL pairs to the complementary DL pair.
  5. The memory device (400) of claim 1, characterized in that a pre-charge mode of the first SRAM array (102) comprises a first phase and a second phase following the first phase; during a period (T1) of the first phase, the first multiplexer circuit (110) connects the at least one of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) to the complementary DL pair (DL, DLB), and the pre-charge circuit (112) is disabled; and during a period (T2) of the second phase, the first multiplexer circuit (110) keeps connecting the at least one of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) to the complementary DL pair (DL, DLB), and the pre-charge circuit (112) is enabled.
  6. The memory device (400) of claim 5, characterized in that the memory device (400) further comprises: a tunable delay circuit (402), configured to control a start time of the second phase.
  7. The memory device (100, 320, 400) of claim 1, characterized in that the pre-charge circuit (600) comprises: a plurality of pre-charge sub-circuits (602_0, 602_1), configured to apply different pre-charge strengths, respectively; wherein at least one of the plurality of pre-charge sub-circuits (602_0, 602_1) is enabled during a period of a pre-charge mode of the first SRAM array (102, 304).
  8. The memory device (100, 320, 400) of claim 7, characterized in that during the period of the pre-charge mode of the first SRAM array (102, 304), only one of the plurality of pre-charge sub-circuits (602_0, 602_1) is enabled.
  9. The memory device (100, 320, 400) of claim 7, characterized in that during the period of the pre-charge mode of the first SRAM array (102, 304), at least two of the plurality of pre-charge sub-circuits (602_0, 602_1) are enabled sequentially.
  10. The memory device (100, 320, 400) of claim 9, characterized in that the at least two of the plurality of pre-charge sub-circuits (602_0, 602_1) comprise a first pre-charge sub-circuit (602_0) and a second pre-charge sub-circuit (602_1), a pre-charge strength of the second pre-charge sub-circuit (602_1) is higher than a pre-charge strength of the first pre-charge sub-circuit (602_0), and the second pre-charge sub-circuit (602_1) is enabled later than the first pre-charge sub-circuit (602_0).
  11. The memory device (100, 320, 400) of claim 1, characterized in that the first multiplexer circuit (110, 322) is used to connect one of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) to the complementary DL pair (DL, DLB) during a period of a read/write mode of the first SRAM array (102, 304), and is reused as a BL pre-charge circuit of at least one of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]) during a period of a pre-charge mode of the first SRAM array (102, 304).
  12. The memory device (100, 320, 400) of claim 11, characterized in that during the period of the pre-charge mode of the first SRAM array (102, 304), the first multiplexer circuit (110, 322) is used as a BL pre-charge circuit of each of the plurality of first complementary BL pairs (BL[0], BLB[0], BL[1], BLB[1]).
  13. The memory device (320) of claim 11, characterized in that the memory device (320) further comprises: a second SRAM array (306), comprising a plurality of second SRAM cells coupled to a plurality of second complementary BL pairs, respectively; and a second multiplexer circuit (324), coupled between the plurality of second complementary BL pairs and the complementary DL pair, wherein the second multiplexer circuit (324) is used to connect one of the plurality of second complementary BL pairs to the complementary DL pair during a period of a read/write mode of the second SRAM array (306), and is reused as a BL pre-charge circuit of at least one of the plurality of second complementary BL pairs during a period of a pre-charge mode of the second SRAM array (306).
  14. The memory device (320) of claim 13, characterized in that during the period of pre-charge mode of the first SRAM array (304), the first multiplexer circuit (322) is used as a BL pre-charge circuit of each of the plurality of first complementary BL pairs; and during the period of the pre-charge mode of the second SRAM array (306) that does not overlap the period of the pre-charge mode of the first SRAM array (304), the second multiplexer circuit (324) is used as a BL pre-charge circuit of each of the plurality of second complementary BL pairs.
  15. The memory device (400) of claim 11, characterized in that the pre-charge mode of the first SRAM array (102) comprises a first phase and a second phase following the first phase; during a period (T1) of the first phase, the BL pre-charge circuit (110) is enabled, and the DL pre-charge circuit (112) is disabled; and during the period (T2) of the second phase, the BL pre-charge circuit (110) keeps enabled, and the DL pre-charge circuit (112) is enabled.

Description

Field of the Invention The present invention relates to a memory design, and more particularly, to a static random access memory (SRAM) device with a pre-charge circuit shared between data lines (DLs) and bit lines (BLs). Background of the Invention For a variety of system on a chip (SoC) applications, a cache storage element can be used to temporarily retain data for further processing. The conventional approach for this cache storage element is using SRAM bit-cells. Each of BLs and DLs needs to be pre-charged to a reference voltage after a read/write (R/W) operation. In a conventional SRAM peripheral circuit design, BLs are pre-charged by dedicated local pre-charge circuits, resulting in high area overhead. Furthermore, high peak current during the BL pre-charge period may induce electro-migration and IR drop issues. To pursue better performance, memory density becomes larger, which makes the SRAM area occupy a big portion of the total chip area. However, it is difficult to shrink SRAM bit-cells in advanced semiconductor process technology. Thus, there is a need for an innovative SRAM peripheral circuit design which can have smaller pre-charge circuit area and/or lower pre-charge peak current. Summary of the Invention This in mind, the present invention aims at providing an SRAM device with a pre-charge circuit shared between DLs and BLs to achieve smaller pre-charge circuit area and/or lower pre-charge peak current. This is achieved by an SRAM device according to the independent claim. The dependent claims pertain to corresponding further developments and improvements. As will be seen more clearly from the detailed description following below, the claimed memory device includes a first SRAM array, a first multiplexer circuit, and a pre-charge circuit. The first SRAM array includes a plurality of first SRAM cells coupled to a plurality of first complementary BL pairs, respectively. The first multiplexer circuit is coupled between the plurality of first complementary BL pairs and a complementary DL pair. The pre-charge circuit is configured to pre-charge the complementary DL pair, and is further configured to pre-charge at least one of the plurality of first complementary BL pairs through the first multiplexer circuit. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof FIG. 1 is a diagram illustrating a first memory design according to an embodiment of the present invention,FIG. 2 is a diagram illustrating waveforms of signals in a memory device shown in FIG. 1,FIG. 3 is a diagram illustrating a floorplan comparison between a conventional memory design and a proposed memory design,FIG. 4 is a diagram illustrating a second memory design according to an embodiment of the present invention,FIG. 5 is a diagram illustrating waveforms of signals in a memory device shown in FIG. 4,FIG. 6 is a diagram illustrating a DL pre-charge circuit with an adjustable pre-charge strength according to an embodiment of the present invention, andFIG. 7 is a diagram illustrating different use cases of the DL pre-charge circuit shown in FIG. 6. Detailed Description Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to ...". Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. FIG. 1 is a diagram illustrating a first memory design according to an embodiment of the present invention. For example, the memory device 100 is an SRAM device that may be used as an SRAM cache in an SoC design. As shown in FIG. 1, the memory device 100 includes an SRAM array 102 and a peripheral circuit 104. The SRAM array 102 includes a plurality of SRAM cells (also called SRAM bit-cells) arranged in a two-dimensional (2D) array with a plurality of rows and a plurality of columns. As shown in FIG. 1, the 1st SRAM cell column may include N+1 SRAM cells 106_0-106_N, and the 2nd SRAM cell column may include N+1 SRAM cells 108_0-108_N, where SRAM cells 106_0 and 108_0 are located at the 1st SRAM cell row, and the SRAM cells 106_N and 108_N are located at the (N+1)th SRAM cell row. It should be noted that the SRAM array 102 may include more than four SRAM cells, more than two SRAM cell columns, and more than two SRAM cell rows. For brevity and simplici