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EP-4738360-A1 - MULTI-PORT STATIC RANDOM ACCESS MEMORY CELL HAVING WRITE WORD LINE OR READ WORD LINE ASSERTED MORE THAN ONCE DURING ONE CLOCK CYCLE AND ASSOCIATED STATIC RANDOM ACCESS MEMORY WITH MULTI-PORT STATIC RANDOM ACCESS MEMORY CELLS

EP4738360A1EP 4738360 A1EP4738360 A1EP 4738360A1EP-4738360-A1

Abstract

A multi-port static random access memory, SRAM, cell (200) includes a storage circuit (206), a plurality of write port circuits (202_1, 202_2, 202_M'), and a plurality of read port circuits (204_1, 204_2, 204_N'). The storage circuit (206) is used to store one bit. The write port circuits (202_1, 202_2, 202_M') are coupled to a first node of the storage circuit (206). Each of the write port circuits (202_1, 202_2, 202_M') is coupled to a write word line, WWL, and a write bit line, WBL. The read port circuits (204_1, 204_2, 204_N') are coupled to a second node of the storage circuit (206). Each of the read port circuits (204_1, 204_2, 204_N') is coupled to a read word line, RWL, and a read bit line, RBL. The WWL or the RWL is asserted more than once during a clock cycle of a clock.

Inventors

  • HONG, CHI-HAO

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260506
Application Date
20251027

Claims (13)

  1. A multi-port static random access memory, SRAM, cell (200) characterized by : a storage circuit (206), configured to store one bit; a plurality of write port circuits (202_1, 202_2, 202_M'), coupled to a first node (Q) of the storage circuit (206), wherein each of the plurality of write port circuits (202_1, 202_2, 202_M') is coupled to a write word line, WWL, and a write bit line, WBL, and a plurality of read port circuits (204_1, 204_2, 204_N'), coupled to a second node (QB) of the storage circuit (206), wherein each of the plurality of read port circuits (204_1, 204_2, 204_N') is coupled to a read word line, RWL, and a read bit line, RBL, wherein the WWL (WWL_1, WWL_2, WWL_M') or the RWL (RWL_1, RWL_2, RWL_N') is asserted more than once during a clock cycle of a clock.
  2. The multi-port SRAM cell (200) of claim 1, characterized in that the WWL (WWL_1, WWL_2, WWL_M') is asserted twice during the clock cycle.
  3. The multi-port SRAM cell (200) of claim 1, characterized in that the RWL (RWL_1, RWL_2, RWL_N') is asserted twice during the clock cycle.
  4. The multi-port SRAM cell (200) of claim 1, characterized in that each of the plurality of write port circuits (202_1, 202_2, 202_M') comprises: an inverter circuit (212), having an input node and an output node; and a transmission gate (214), comprising: a first metal-oxide-semiconductor, MOS, transistor (216), having a control terminal, a first connection terminal, and a second connection terminal; and a second MOS transistor (218), having a control terminal, a first connection terminal, and a second connection terminal; wherein the input node of the inverter circuit (212) is coupled to the WWL (WWL_1) and the control terminal of the first MOS transistor (216), the output node of the inverter circuit (212) is coupled to the control terminal of the second MOS transistor (218), the first connection terminal of the first MOS transistor (216) and the first connection terminal of the second MOS transistor (218) are coupled to the WBL (WBL_1), and the second connection terminal of the first MOS transistor (216) and the second connection terminal of the second MOS transistor (218) are coupled to the first node (Q) of the storage circuit (206).
  5. The multi-port SRAM cell (200) of claim 1, characterized in that the storage circuit (206) is a feedback latch circuit with a feedback loop (210), the plurality of write port circuits (202_1, 202_2, 202_M') are coupled to a plurality of WWLs (WWL_1, WWL_2, WWL_M'), respectively, and the multi-port SRAM cell (200) further comprises: a logic circuit (208), having a plurality of input nodes coupled to the plurality of WWLs (WWL_1, WWL_2, WWL_M'), respectively, wherein the logic circuit (208) is configured to generate at least one control signal (WWLCUT, WWLBCUT) which determines whether to cut off the feedback loop (210).
  6. A static random access memory, SRAM, (100) characterized by : a memory array (102), comprising: a plurality of SRAM cells (106), each being implemented by the multi-port SRAM cell (200) of claim 1; and a peripheral circuit (104), configured to control access of the plurality of SRAM cells (106) in the memory array (102).
  7. The SRAM (100) of claim 6, characterized in that the WWL (WWL_1, WWL_2, WWL_M') is asserted twice during the clock cycle.
  8. The SRAM (100) of claim 7, characterized in that the peripheral circuit (104) comprises: a plurality of data-in, DI, circuits (402_1, 402_M'), coupled to the plurality of write port circuits, respectively, wherein each of the plurality of DI circuits (402_1, 402_M') includes: a first digital circuit (404), configured to store a first bit to be provided to a write port circuit; a second digital circuit (406), configured to store a second bit to be provided to the write port circuit; and a multiplexer circuit (408), having a first input node, a second input node, and an output node, wherein the first input node is coupled to the first digital circuit (404), the second input node is coupled to the second digital circuit (406), and the output node is configured to output the first bit during a first phase of the clock cycle and output the second bit during a second phase of the clock cycle.
  9. The SRAM (100) of claim 8, characterized in that the first digital circuit (404) and the second digital circuit (406) are both triggered by a rising edge of the clock; or the first digital circuit (404) is triggered by a rising edge of the clock, and the second digital circuit (406) is triggered by a falling edge of the clock.
  10. The SRAM (100) of claim 8, characterized in that the first digital circuit (404) is a latch circuit, and the second digital circuit (406) is a D-type flip-flop circuit; or both of the first digital circuit (404) and the second digital circuit (406) are latch circuits.
  11. The SRAM (100) of claim 6, characterized in that the RWL (RWL_1, RWL_2, RWL_N') is asserted twice during the clock cycle.
  12. The SRAM (100) of claim 11, characterized in that the peripheral circuit (104) comprises: a plurality of data-out, DO, circuits (502_1, 502_N'), coupled to the plurality of read port circuits (204_1, 204_2, 204_N'), respectively, wherein each of the plurality of DO circuits (502_1, 502_N') includes: a first digital circuit (504), configured to store one bit output from a read port circuit during a first phase of the clock cycle; and a second digital circuit (506), configured to store one bit output from the read port circuit during a second phase of the clock cycle.
  13. The SRAM (100) of claim 12, characterized in that both of the first digital circuit (504) and the second digital circuit (506) are latch circuits; or the first digital circuit (504) is a latch circuit, and the second digital circuit (506) is a D-type flip-flop circuit; or both of the first digital circuit (504) and the second digital circuit (506) are D-type flip-flop circuits.

Description

Field of the Invention The present invention relates to a static random access memory (SRAM) design, and more particularly, to a multi-port SRAM cell having a write word line (WWL) and/or a read word line (RWL) asserted more than once during one clock cycle and an associated SRAM with multi-port SRAM cells. Background of the Invention In high speed computers and digital signal processors, multiport SRAMs are essential components, especially in modern multi-core system on a chip (SoC). For example, a conventional multi-port SRAM cell that allows simultaneous N read operations/M write operations is required to have N read ports and M write ports. When the numbers of read ports and write ports are increased to meet requirements of high speed applications, a conventional SRAM with multi-port SRAM cells requires a larger die area, which increases the area and the power consumption of the SOC. Thus, there is a need for an innovative multi-port SRAM cell design which provides simultaneous N read operations by using N' (N' < N) read ports and provides simultaneous M write operations by using M' (M' < M) write ports. Summary of the Invention This in mind, the present invention aims at providing a multi-port SRAM cell having a WWL and/or an RWL asserted more than once during one clock cycle and an associated SRAM with multi-port SRAM cells. This is achieved by the multi-port SRAM cell and the SRAM according to the independent claims. The dependent claims pertain to corresponding further developments and improvements. As will be seen more clearly from the detailed description following below, the claimed multi-port SRAM cell includes a storage circuit, a plurality of write port circuits, and a plurality of read port circuits. The storage circuit is configured to store one bit. The write port circuits are coupled to a first node of the storage circuit. Each of the write port circuits is coupled to a write word line (WWL) and a write bit line (WBL). The read port circuits are coupled to a second node of the storage circuit. Each of the read port circuits is coupled to a read word line (RWL) and a read bit line (RBL). The WWL or the RWL is asserted more than once during a clock cycle of a clock. In addition, the claimed SRAM includes a memory array and a peripheral circuit. The memory array includes a plurality of SRAM cells, each being implemented by the claimed multi-port SRAM cell. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof FIG. 1 is a diagram illustrating an SRAM design according to an embodiment of the present invention,FIG. 2 is a diagram illustrating a multi-port SRAM cell design according to an embodiment of the present invention,FIG. 3 is a diagram illustrating waveforms of WWL signals and RWL signals used by a double-pumped 4R4W multiport-SRAM cell according to an embodiment of the present invention,FIG. 4 is a diagram illustrating a DI circuit design according to an embodiment of the present invention, andFIG. 5 is a diagram illustrating a DO circuit design according to an embodiment of the present invention. Detailed Description Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to ...". Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. FIG. 1 is a diagram illustrating an SRAM design according to an embodiment of the present invention. The SRAM 100 includes a memory array 102 and a peripheral circuit 104. The memory array 102 includes a plurality of multi-port SRAM cells (also called bit-cells) 106 arranged in a two-dimensional (2D) array with a plurality of rows and a plurality of columns. Each of the multi-port SRAM cells 106 has the proposed multi-port SRAM cell design. The peripheral circuit 104 acts as an input/output (I/O) circuit used to control access (read/write) of the multi-port SRAM cells 106 in the memory array 102. For example, the peripheral circuit 104 may include a row decoder, a timing controller, a column decoder, a sense amplifier, etc. FIG. 2 is a diagram illustrating a multi-port SRAM cell design according to an embodiment of the present invention. Each of the multi-port SRAM cells 106 shown in FIG. 1 may be implemented using the multi-port SRAM cell 200 shown in FIG.