EP-4738361-A2 - CONFIGURATION BIT HAVING A PLURALITY OF MAGNETORESISTIVE DEVICES, AND METHODS OF PROGRAMMING AND READING THE SAME

EP4738361A2EP 4738361 A2EP4738361 A2EP 4738361A2EP-4738361-A2

Abstract

A method for programming a configuration bit including magnetic tunnel junctions (MTJs), including during a first phase: applying a first voltage to a first leg of MTJs and a third leg of MTJs to program or inhibit the MTJs of the first leg and the third leg, and applying a second voltage to a second leg of MTJs and a fourth leg of MTJs to program or inhibit the MTJs of the second leg and the fourth leg. During a second phase: applying the second voltage to the first leg of MTJs and the third leg of MTJs to program or inhibit the MTJs of the first leg and the third leg, and applying the first voltage to the second leg of MTJs and the fourth leg of MTJs to program or inhibit the MTJs of the second leg and the fourth leg.

Inventors

SADD, MICHAEL A.
ALBRIGHT, Keith
ALAM, SYED M.
HUTCHISON, BRIAN
DO, Vincent

Assignees

Everspin Technologies, Inc.

Dates

Publication Date: 20260506
Application Date: 20251029

Claims (15)

A method of programming a configuration bit including magnetic tunnel junctions (MTJs), the method comprising: during a first phase: applying a first voltage to a first leg of MTJs and a third leg of MTJs to program or inhibit one or more MTJs of the first leg of MTJs and one or more MTJs of the third leg of MTJs, and applying a second voltage to a second leg of MTJs and a fourth leg of MTJs to program or inhibit one or more MTJs of the second leg of MTJs and one or more MTJs of the fourth leg of MTJs, and during a second phase: applying the second voltage to the first leg of MTJs and the third leg of MTJs to program or inhibit the one or more MTJs of the first leg of MTJs and the one or more MTJs of the third leg of MTJs, and applying the first voltage to the second leg of MTJs and the fourth leg of MTJs to program or inhibit the one or more MTJs of the second leg of MTJs and the one or more MTJs of the fourth leg of MTJs.
The method of claim 1, wherein inhibiting the one or more MTJs of the first leg of MTJs, the one or more MTJs of the second leg of MTJs, the one or more MTJs of the third leg of MTJs, or the one or more MTJs of the fourth leg of MTJs comprises: maintaining a state of each of the one or more MTJs of the first leg of MTJs, the one or more MTJs of the second leg of MTJs, the one or more MTJs of the third leg of MTJs, or the one or more MTJs of the fourth leg of MTJs.
The method of any of the preceding claims, wherein programming the one or more MTJs of the first leg of MTJs, the one or more MTJs of the second leg of MTJs, the one or more MTJs of the third leg of MTJs, or the one or more MTJs of the fourth leg of MTJs comprises: changing a state of each of the one or more MTJs of the first leg of MTJs, the one or more MTJs of the second leg of MTJs, the one or more MTJs of the third leg of MTJs, or the one or more MTJs of the fourth leg of MTJs.
The method of any of the preceding claims, wherein the first voltage and the second voltage are different.
The method of any of the preceding claims, wherein, during the first phase, a state of the one or more MTJs of the second leg of MTJs and a state of the one or more MTJs of the fourth leg of MTJs change in response to applying the second voltage and/or wherein, during the second phase, a state of the one or more MTJs of the first leg of MTJs and a state of the one or more MTJs of the third leg of MTJs change in response to applying the second voltage.
The method of any of the preceding claims, wherein, during the first phase, a state of the one or more MTJs of the first leg of MTJs and a state of the one or more MTJs of the third leg of MTJs are maintained in response to applying the first voltage; and during the second phase, a state of the one or more MTJs of the second leg of MTJs and a state of the one or more MTJs of the fourth leg of MTJs are maintained in response to applying the first voltage.
The method of any of the preceding claims, wherein one of the first voltage or the second voltage is approximately 0 and the other of the first voltage or the second voltage is a supply voltage, and/or wherein each of the first leg of MTJs, the second leg of MTJs, the third leg of MTJs, and the fourth leg of MTJs is connected to a corresponding pair of write drivers.
A storage device, comprising: a configuration bit including: a first leg of magnetic tunnel junctions (MTJs); and a second leg of MTJs; wherein each of the first leg of MTJs and the second leg of MTJs includes at least four MTJs, and wherein the configuration bit is configured to program at least two MTJs in each of the first leg of MTJs and the second leg of MTJs while simultaneously inhibiting from programming at least two other MTJs in each of the first leg of MTJs and the second leg of MTJs, the storage device, in particular, further comprising: a plurality of drivers including a first driver, a second driver, a third driver, a fourth driver, and a fifth driver, wherein the first leg of MTJs is connected to the first driver, the second driver, and the third driver, and wherein the second leg of MTJs is connected to the third driver, the fourth driver, and the fifth driver.
The storage device of claim 8, wherein the configuration bit is configured to program the at least two MTJs in each of the first leg of MTJs and the second leg of MTJs based on applying different voltages across the at least two MTJs in each of the first leg of MTJs and the second leg of MTJs.
The storage device of claim 8, wherein the configuration bit is configured to inhibit from programming the at least two other MTJs in each of the first leg of MTJs and the second leg of MTJs based on applying same voltages across the at least two other MTJs in each of the first leg of MTJs and the second leg of MTJs, and/or wherein the configuration bit is configured to program the at least two MTJs in each of the first leg of MTJs and the second leg of MTJs based on changing a state of the at least two MTJs in each of the first leg of MTJs and the second leg of MTJs to a high resistance state or a low resistance state.
The storage device of claim 8, wherein the configuration bit is configured to inhibit from programming the at least two other MTJs in each of the first leg of MTJs and the second leg of MTJs based on maintaining a state of the at least two other MTJs in each of the first leg of MTJs and the second leg of MTJs.
A memory device, comprising: a program circuit, wherein the program circuit includes one or more configuration bits, wherein each of the one or more configuration bits includes one or more magnetic tunnel junctions (MTJs); a read circuit, wherein the read circuit includes one or more latching devices; a poly arrangement; and a diffusion area, wherein the read circuit is disposed perpendicular to the program circuit.
The memory device of claim 12, wherein the poly arrangement includes polysilicon interconnections, and wherein the diffusion area includes an active region covering at least a portion of the one or more configurations bits, in particular, wherein, by disposing the read circuit perpendicular to the program circuit, a total area of the program circuit and the read circuit within the memory device is reduced.
The memory device of claim 12 or 13, wherein the diffusion area includes a height and a width, and wherein the height of the diffusion area is maintained and the width of the diffusion area is adjusted to increase an active region between the program circuit and the read circuit.
The memory device of any of claims 12, 13, or 14, wherein the read circuit is mis-match sensitive allowing for a length and a width of each of the one or more latching devices to be adjusted to increase an active region of the diffusion area.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims benefit to U.S. Non-Provisional Patent Application No. 19/370,982, filed October 28, 2025, which claims priority to U.S. Provisional Patent Application No. 63/713,797 filed October 30, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates generally to systems and methods for a memory device, and, more particularly, programming configuration bits of a memory device. INTRODUCTION Each integrated circuit chip may include billions of devices thereon, including memory devices such as magnetoresistive tunnel junctions (MTJs). Memory devices may include configuration bits that utilize MTJs to store configuration data for controlling various circuit operations. Each configuration bit may include multiple MTJs arranged in legs, where each leg contains one or more MTJs connected in series. Programming configuration bits may involve applying voltages to simultaneously program multiple legs of MTJs, which may require drivers and circuit components to handle increased current loads when multiple legs are programmed concurrently. When programming multiple legs of MTJs simultaneously, drivers connected to shared nodes between legs may need to support current drawn by more than one leg at the same time. This may require larger driver components capable of handling the increased current, which may result in increased circuit area and higher power consumption. Additionally, MTJs may experience defects during the manufacturing process, or may experience damage throughout the lifetime of the device, that may adversely affect the operation of a memory device. Defects or damage may include, for example, short or open defects. A short defect causes unintentional electrical contact between layers of an MTJ (e.g., the MTJ may constantly conduct electrical current), while an open defect causes an MTJ to act as an open switch (e.g., no electrical conduction therein). Both short and open defects can adversely affect or destroy MTJ performance. The need for larger components to support simultaneous programming of multiple MTJ legs may adversely affect the overall efficiency and area utilization of memory devices. Therefore, it may be desirable to have configuration bit designs that can reduce the current requirements for individual drivers while maintaining programming functionality. Furthermore, it may be desirable to achieve such designs in a manner that allows for smaller component sizes and reduced overall circuit area without requiring enlarged components. BRIEF DESCRIPTION OF DRAWINGS In the course of the detailed description that follows, reference will be made to the appended drawings. The drawings show different aspects of the present disclosure and, where appropriate, reference numerals illustrating like structures, components, materials, and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, and/or elements, other than those specifically shown, are contemplated and are within the scope of the present disclosure. Moreover, there are many embodiments of the present disclosure described and illustrated herein. The present disclosure is neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present disclosure, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present disclosure and/or embodiments thereof. For the sake of brevity, certain permutations and combinations are not discussed and/or illustrated separately herein; however, all permutations and combinations are considered to fall within the scope of the present inventions. FIG. 1 depicts an exemplary circuit schematic of a configuration bit, according to one or more embodiments.FIG. 2 depicts an exemplary configuration bit implementing a two-pass program for area reduction, according to one or more embodiments.FIG. 3 depicts an exemplary configuration bit implementing a two-pass program for area reduction, according to one or more embodiments.FIGS. 4A and 4B depict plot measurements corresponding to a two-pass program of FIGS. 2-3, according to one or more embodiments.FIG. 5 depicts a layout of a configuration bit with write circuit perpendicular to read circuit. Again, there are many embodiments described and illustrated herein. The present disclosure is neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Each of the aspects of the present disclosure, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present disclosure and/or embodiments thereof. For the sake of brevity, many of those combinations and permutations are not discussed sep