EP-4738362-A1 - CAPACITOR-LESS MEMORY DEVICE

EP4738362A1EP 4738362 A1EP4738362 A1EP 4738362A1EP-4738362-A1

Abstract

A capacitor-less memory device according to an aspect of the present invention may include a memory cell comprising a write transistor including a first gate, a first drain, and a first source, and a read transistor including a second gate, a second drain, a second source, and a back gate, wherein the second drain is connected to the first drain and the second gate is connected to the first source to operate as a storage node. A bit line may be commonly connected to the first drain and the second drain, a word line may be connected to the first gate, and a control line may be connected to the back gate. The read transistor may be turned on or turned off depending on a data state of the storage node or a control voltage applied to the control line.

Inventors

KANG, DAE HWAN
RYU, YONG WOO

Assignees

POSTECH Research and Business Development Foundation

Dates

Publication Date: 20260506
Application Date: 20251029

Claims (15)

A capacitor-less memory device comprising: a memory cell including a write transistor having a first gate, a first drain, and a first source, and a read transistor having a second gate, a second drain, a second source, and a back gate, wherein the second gate is connected to the first source to operate as a storage node; a bit line commonly connected to the first drain and the second drain; a word line connected to the first gate; a control line connected to the back gate; and a select line connected to the second source, wherein the read transistor is turned on or turned off depending on a data state of the storage node or a control voltage applied to the control line.
The capacitor-less memory device of claim 1, wherein, to store a first data state in the storage node of the memory cell, a write operation voltage is applied to the bit line and the word line, an off voltage or a precharge voltage is applied to the control line, and a precharge voltage or a write operation voltage is applied to the select line.
The capacitor-less memory device of claim 1 or 2, wherein, to store a second data state in the storage node of the memory cell, a write operation voltage is applied to the word line, an off voltage is applied to the bit line, an off voltage or a precharge voltage is applied to the control line, and a precharge voltage or an off voltage is applied to the select line.
The capacitor-less memory device of any one of claims 1 to 3, wherein, to read a data state of the memory cell, an off voltage is applied to the word line and the control line, an off voltage is applied to the select line, and a degree of voltage drop is sensed at the bit line.
A capacitor-less memory device comprising: a plurality of vertically stacked memory cells, the plurality of memory cells including a plurality of write transistors each having a first gate, a first drain, and a first source, and a plurality of read transistors each having a second gate, a second drain, a second source, and a back gate, wherein the second gate is connected to the first source to operate as a storage node, the plurality of read transistors being connected vertically to one another; a bit line connected to the first drain of the plurality of memory cells and to the second drain of an uppermost one of the plurality of read transistors; a plurality of word lines respectively connected to the first gates of the plurality of memory cells; a plurality of control lines respectively connected to the back gates of the plurality of memory cells; and a select line connected to the second source of a lowermost one of the plurality of read transistors, wherein each read transistor is turned on or turned off depending on a data state of the storage node or a control voltage applied to the back gate.
The capacitor-less memory device of claim 5, wherein, to store a first data state in the storage node of a selected one of the plurality of memory cells, a write operation voltage is applied to the bit line, a write operation voltage is applied to the word line connected to the selected memory cell among the plurality of word lines, an off voltage is applied to the remaining word lines, an off voltage or a precharge voltage is applied to the control line, and a precharge voltage or a write operation voltage is applied to the select line.
The capacitor-less memory device of claim 5 or 6, wherein, to store a second data state in the storage node of a selected one of the plurality of memory cells, an off voltage is applied to the bit line, a write operation voltage is applied to the word line connected to the selected memory cell among the plurality of word lines, an off voltage is applied to the remaining word lines, an off voltage or a precharge voltage is applied to the control line, and a precharge voltage or an off voltage is applied to the select line.
The capacitor-less memory device of any one of claims 5 to 7, wherein, to read a data state of a selected one of the plurality of memory cells, an off voltage is applied to the plurality of word lines, an off voltage is applied to the control line connected to the back gate of the selected memory cell among the plurality of control lines, a precharge voltage is applied to the remaining control lines, an off voltage is applied to the select line, and a degree of voltage drop is sensed at the bit line.
A capacitor-less memory device comprising: \\\ a plurality of first semiconductor layers stacked on a substrate and spaced apart from each other; a plurality of first gate electrode layers disposed between the plurality of first semiconductor layers; a first gate insulating layer interposed between the plurality of first semiconductor layers and the plurality of first gate electrode layers; a plurality of first drain electrode layers respectively connected to sides of the plurality of first semiconductor layers; a plurality of first source electrode layers respectively connected to opposite sides of the plurality of first semiconductor layers; a plurality of second gate electrode layers respectively connected to the plurality of first source electrode layers; a second semiconductor layer extending vertically across the plurality of second gate electrode layers; a plurality of back gate electrode layers respectively disposed on sides of the second semiconductor layer opposite to the plurality of second gate electrode layers; a second gate insulating layer interposed between the plurality of second gate electrode layers and the second semiconductor layer and between the plurality of back gate electrode layers and the second semiconductor layer; a plurality of word lines respectively connected to the plurality of first gate electrode layers; and a bit line connected to the plurality of first drain electrode layers and connected to an upper end of the second semiconductor layer, wherein the plurality of second gate electrode layers are respectively used as a plurality of storage nodes.
The capacitor-less memory device of claim 9, wherein the bit line comprises: a vertical electrode extending vertically to be connected to the plurality of first drain electrode layers; and a horizontal electrode extending horizontally to be connected to an upper end of the second semiconductor layer and connected to the vertical electrode.
The capacitor-less memory device of claim 9 or 10, wherein the first source electrode layer and the second gate electrode layer disposed in the same layer among the plurality of first source electrode layers and the plurality of second gate electrode layers are integrally formed with each other.
The capacitor-less memory device of any one of claims 9 to 11, wherein portions of the second semiconductor layer facing the plurality of second gate electrode layers function as channel layers, and portions of the second semiconductor layer between the channel layers function as second drain electrode layers or second source electrode layers.
The capacitor-less memory device of any one of claims 9 to 12, wherein each of the plurality of first semiconductor layers has a planar shape, and the second semiconductor layer has a pillar shape.
The capacitor-less memory device of any one of claims 9 to 13, wherein the plurality of first semiconductor layers and the second semiconductor layer comprise an oxide semiconductor material.
The capacitor-less memory device of any one of claims 9 to 14, further comprising an interlayer insulating layer on the substrate; and via electrodes formed in the interlayer insulating layer to connect the substrate and a lower end of the second semiconductor layer or to connect the substrate and the bit line.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION This application claims the benefit under 35 U.S.C. § 119 of Korean Patent Application Nos. 10-2024-0153634, filed on November 1, 2024, and 10-2025-0088693, filed on July 2, 2025, the disclosure of which is hereby incorporated by reference in its entirety. This invention was supported by the research project funded by the Ministry of Trade, Industry and Energy and the Korea Planning & Evaluation Institute of Industrial Technology, under Project Unique Number 2410000277 and Project Number 00235402. BACKGROUND 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a memory device capable of storing data without a capacitor. 2. Description of the Related Art In general, memory devices can be classified into volatile devices, in which data disappears when power is turned off, and non-volatile devices, in which data is retained even when power is turned off. Among volatile devices, a dynamic random access memory (DRAM) device typically stores data by using a capacitor, and research has been conducted to increase data capacity by increasing the capacitance of the capacitor. A typical DRAM device forms a memory cell with one transistor and one capacitor (1T-1C). However, in the DRAM device, as the volume of the capacitor increases, there is a limitation in improving integration density, and the difficulty of manufacturing also significantly increases. Accordingly, research has been conducted on a capacitor-less DRAM capable of operating in the same manner as a conventional DRAM device without a capacitor. Conventionally, a capacitor-less DRAM device implements a memory operation with two transistors (2T-0C) without a capacitor. However, when the device is implemented in a planar type, a relatively large cell area is still required, and a process of three-dimensionally stacking the device to improve integration density is difficult to achieve. In addition, when the device is implemented in a vertical type, although there is an advantage in that the area can be reduced, it is still difficult to perform a three-dimensional stacking process to further improve integration density. SUMMARY OF THE INVENTION The present invention has been made to address the above-described and other problems, and it is an object of the present invention to provide a capacitor-less memory device capable of achieving high integration and facilitating a stacking process. However, such an object is merely exemplary, and the scope of the present invention should not be limited thereby. According to an aspect of the present invention, a capacitor-less memory device may include a memory cell comprising a write transistor including a first gate, a first drain, and a first source, and a read transistor including a second gate, a second drain, a second source, and a back gate, wherein the second drain is connected to the first drain and the second gate is connected to the first source to operate as a storage node. A bit line may be commonly connected to the first drain and the second drain, a word line may be connected to the first gate, and a control line may be connected to the back gate. The read transistor may be turned on or turned off depending on a data state of the storage node or a control voltage applied to the control line. In the capacitor-less memory device, to store a first data state in the storage node of the memory cell, a write operation voltage may be applied to the bit line and the word line, and a precharge voltage or an off voltage may be applied to the control line. In the capacitor-less memory device, to store a second data state in the storage node of the memory cell, a write operation voltage may be applied to the word line, an off voltage may be applied to the bit line, and a precharge voltage or an off voltage may be applied to the control line. In the capacitor-less memory device, to read a data state of the memory cell, an off voltage may be applied to the word line and the control line, and a degree of voltage drop may be sensed at the bit line. The capacitor-less memory device may further include a select line connected to the second source. In the capacitor-less memory device, to store a first data state in the storage node of the memory cell, a write operation voltage may be applied to the bit line and the word line, an off voltage or a precharge voltage may be applied to the control line, and a precharge voltage or a write operation voltage may be applied to the select line. In the capacitor-less memory device, to store a second data state in the storage node of the memory cell, a write operation voltage may be applied to the word line, an off voltage may be applied to the bit line, an off voltage or a precharge voltage may be applied to the control line, and a precharge voltage or an off voltage may be applied to the select line. In the capacitor-less memory device, to read a data state of the memory cell, an off