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EP-4738364-A1 - NON-VOLATILE MEMORY WITH ERROR CORRECTION

EP4738364A1EP 4738364 A1EP4738364 A1EP 4738364A1EP-4738364-A1

Abstract

In a non-volatile memory (NVM), a memory array has a differential bit cell at each row and column intersection, in which each row stores an N-bit data element and a single parity bit corresponding to the data element. Each differential bit cell includes a first and a second single-ended bit cell, and a logic state is determined by the logic states of the first and second single-ended bit cells. A read operation includes providing, from the differential bit cells of the selected row, differential read data having an N-bit data value and a corresponding single bit parity value, and providing logic states of each of the first and second single-ended bit cells of the differential bit cells of the selected row. Based on the logic states of the first and second single-ended bit cells, a read event flag and a multiple event flag are generated for the read operation.

Inventors

  • STORMS, MAURITS MARIO NICOLAAS
  • REBOLLO PIMENTEL, IVAN JESUS
  • ZACHARIASSE, FRANK
  • VAN STRAATEN, BRAM
  • de Meulmeester, Jacobus

Assignees

  • NXP B.V.

Dates

Publication Date
20260506
Application Date
20251022

Claims (13)

  1. A non-volatile memory (NVM), comprising: a memory array arranged in rows and columns and having a differential bit cell at each row and column intersection, wherein each row is configured to store an N-bit data element and a single parity bit corresponding to the data element, and each differential bit cell includes: a first single-ended bit cell having a storage element configured to store a logic state of the first single-ended bit cell, and a second single-ended bit cell having a storage element configured to store a logic state of the second single-ended bit cell, wherein a logic state of the differential bit cell is determined by the logic states of the first and second single-ended bit cells; and read circuitry configured to, in response to a read access request, perform a read operation from differential bit cells of a selected row of the memory array, wherein performing the read operation includes: providing, from the differential bit cells of the selected row, differential read data having an N-bit data value and a corresponding single bit parity value, providing logic states of each of the first and second single-ended bit cells of the differential bit cells of the selected row, and generating, based on the logic states of the first and second single-ended bit cells of the differential bit cells, a read event flag and a multiple event flag for the read operation.
  2. The NVM of claim 1, wherein: the read event flag is asserted for the read operation when the logic circuitry detects at least one single ended error, and the multiple event flag is asserted for the read operation when the logic circuitry detects more than one single ended error.
  3. The NVM of claim 2, wherein each column of the array comprises a corresponding bit line pair, wherein, for each column of the memory array, the read circuitry comprises: a differential read-out circuit coupled to the corresponding bit line pair and configured to provide a corresponding differential bit value, a first single-ended read-out circuit coupled to one bit line of the corresponding bit line pair, and configured to provide a corresponding first single-ended read value, a second single-ended read-out circuit coupled to another bit line of the corresponding bit line pair, and configured to provide a corresponding second single-ended read value, and a bit error detection circuit configured to provide a corresponding bit error detection indicator based on the first and second single-ended read values, wherein the bit error detection circuit is configured to assert the corresponding bit error detection indicator when a corresponding single-ended error is indicated.
  4. The NVM of claim 3, wherein the corresponding single-ended error is indicated when the corresponding first single-ended read value matches the corresponding second single-ended read value.
  5. The NVM of claim 3 or 4, wherein the read circuitry further comprises logic circuitry configured to generate the read event flag for the read operation based on the corresponding bit error detection indicators for the columns of the memory array.
  6. The NVM of claim 5, wherein the read event flag for the read operation is generated as a logical OR of the corresponding bit error detection indicators.
  7. The NVM of claim 5 or 6, wherein the logic circuitry is further configured to generate a corresponding corrected differential bit value based the corresponding differential bit value and the corresponding bit error detection indicator.
  8. The NVM of any one of claims 5 to 7, wherein the logic circuitry is further configured to generate the multiple event flag for the read operation based on the corresponding bit error detection indicator of multiple columns.
  9. The NVM of any preceding claim, wherein the providing the logic states of each of the first and second single-ended bit cells of the differential bit cells of the selected row comprises providing an ((N+1)x2)-bit single-ended read value.
  10. The NVM of any preceding claim, wherein the providing the differential read data and the providing the logic states are performed in parallel.
  11. A method of operating a non-volatile memory (NVM), the NVM having a memory array arranged in row and columns and having a differential bit cell at each row and column intersection, wherein each differential bit cell includes a corresponding first single-ended bit cell having a storage element configured to store a logic state of the corresponding first single-ended bit cell a corresponding second single-ended bit cell having a storage element configured to store a logic state of the corresponding second single-ended bit cell, in which a logic state of the differential cell is determined by the logic states of the corresponding first and second single-ended bit cells, the method comprising: receiving a read access request addressing a selected set of differential bit cells of the memory array; and performing a read operation in response to the read access request, wherein the read operation comprises: providing, from the selected set of differential bit cells, differential read data having an N-bit data value and a corresponding single bit parity value, providing single-ended read data having (N+1)x2 bits by providing bit values from each of the corresponding first and corresponding second single-ended bit cells of the selected set of differential bit cells, and providing, based on the bit values from the corresponding first and corresponding second single-ended bit cells of the selected set of differential bit cells, a read event flag and a multiple event flag for the read operation, wherein: the read event flag is asserted for the read operation when the logic circuitry detects at least one single ended error, and the multiple event flag is asserted for the read operation when the logic circuitry detects more than one single ended error.
  12. The method of claim 11, wherein the providing the read event flag for the read operation further comprises: generating a corresponding bit error detection indicator for each differential bit cell of the selected set of differential bit cells by determining whether or not the bit values from each of the corresponding first and corresponding second single-ended bit cells match, wherein the read event flag is generated based on the corresponding bit error detection indicators for the selected set of differential bit cells.
  13. The NVM of claim 12, wherein the read operation further comprises: generating a corresponding corrected differential bit value for each bit of the differential read data based on the bit of the differential read value and the corresponding bit error detection indicator.

Description

Background Field This disclosure relates generally to memories, and more specifically, to a non-volatile memory with error correction. Related Art Error correction (ECC) is a known technique used to enhance data retention in non-volatile memories (NVMs). To implement ECC, multiple error correction bits are stored with each data element in the memory array, in which the number of required error correction bits depends on the length of the data element. For example, with conventional single error correction double error detection (SECDED) ECC, 6 correction bits are needed for each 16-bit word. These multiple correction bits result for each data element in increased area overhead for the NVM as well as increased digital processing for performing ECC. Therefore, a need exists for improved ECC in NVMs with reduced impact on area overhead and ECC processing. Brief Description of the Drawings The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates, in block diagram form, an NVM memory having a memory array of differential bit cells and corresponding read circuitry, in accordance with one embodiment of the present invention.FIG. 2 illustrates, in schematic form, a differential bit cell of the memory array of FIG. 1, in accordance with one embodiment of the present invention.FIG. 3 illustrates, in partial block diagram and partial schematic form, a portion of the read circuitry of FIG. 1, in accordance with one embodiment of the present invention.FIG. 4 illustrates, in diagrammatic form, a row of the memory array of FIG. 1 and a portion of the corresponding read circuitry, in accordance with one embodiment of the present invention. Detailed Description In one aspect, an NVM is provided with SECDED ECC capability, but without requiring the multiple correction bits of traditional ECC for each data element. In this manner, reduced area overhead of the NVM is achieved, as compared to conventional NVMs. The memory array of the NVM is constructed as an array of differential bit cells, in which each differential bit cell is formed by two single-ended bit cells, in which each single-ended bit cell includes a storage element (such as a charge-based storage element implanted as a floating gate transistor). Each read operation from the NVM reads an addressed data element from the differential array, in which each read operation performs both differential reads and single-ended reads. For example, read circuitry coupled to the memory array is configured to provide differential read data from a set of addressed differential bit cells of the array during each read operation, in which each differential bit cell provides one bit of read data. The differential read data also includes a single parity bit, regardless of the length of the addressed data element. During each read operation, the read circuitry is further configured to provide single-ended read data from each of the single-ended cells of the set of addressed differential bit cells. ECC circuitry is configured to use the single-ended read data to detect and indicate a single bit error or multiple bit error for the read operation and to correct a single bit error, if possible. In this manner, an NVM with ECC is provided with reduced area overhead and reduced complexity. FIG. 1 illustrates, in block diagram form, an NVM 100, in accordance with an embodiment of the present invention. NVM 100 includes a memory array 102, column drivers 104, read circuitry 106, row drivers 108, and control circuitry 112. Array 102 is arranged in rows and columns, in which a differential bit cell (e.g. differential bit cell 110) is located at the intersection of each row and column. Array 102 includes M rows and K columns, and thus includes M x K differential bit cells. Each of M and K can be any integer value. In one embodiment, K is 17 (corresponding to a 16-bit data element and a single parity bit, as will be described in more detail below). Each row has a corresponding word line (WL1-WLM) and each column has an corresponding bit line (BL) pair (BL1/BL_N1 - BLK/BL_NK). In the illustrated embodiment, each column also includes a corresponding source line (SL) pair (SL1/SL_N1 - SLK/SL_NK), and each row also includes a control gate line (CGL1-CGLM). Note that for each bit line pair, BL_N corresponds to the complementary bit line (or inverse bit line) to BL, and similarly, for each source line pair, SL_N corresponds to the complementary source line (or inverse source line) of SL. Row drivers 108 are configured to drive the WLs and CGLs, and column drivers 104 are configured to drive the BL pairs and SL pairs. Each differential bit cell is therefore coupled to a corresponding WL, CGL, BL pair, and SL pair. Control circuitry 112 is coupled to row drivers 108, column driver