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EP-4738366-A1 - READ-ONLY MEMORY WITH ONE-TRANSISTOR READ-ONLY MEMORY CELLS AND METHOD FOR WRITING READ-ONLY MEMORY CODE WITH BIT LINE LOAD OPTIMIZATION INTO READ-ONLY MEMORY

EP4738366A1EP 4738366 A1EP4738366 A1EP 4738366A1EP-4738366-A1

Abstract

A read-only memory, ROM, (100) includes a first ROM cell (104), a second ROM cell (106), and a third ROM cell (102). The first ROM cell (104) is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor, MOS, transistor (114). The second ROM cell (106) is configured to store a second data value of the ROM code, and includes a second MOS transistor (116), wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor (114). The third ROM cell (102) is configured to store a third data value of the ROM code, and includes a third MOS transistor (112), wherein a drain node of the third MOS transistor (112) is electrically connected to a source node of the first MOS transistor (114).

Inventors

  • YANG, TZU-HSIEN
  • CHIU, YI-TE

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260506
Application Date
20251029

Claims (15)

  1. A read-only memory, ROM, (100) characterized by : a first ROM cell (104), configured to store a first data value of a ROM code, wherein the first ROM cell (104) comprises: a first meta-oxide-semiconductor, MOS, transistor (114), having a gate node, a source node, and a drain node; a second ROM cell (106), configured to store a second data value of the ROM code, wherein the second ROM cell (106) comprises: a second MOS transistor (116), having a gate node, a source node, and a drain node, wherein the source node of the second MOS transistor (116) is electrically connected to the drain node of the first MOS transistor (114); and a third ROM cell (102), configured to store a third data value of the ROM code, wherein the third ROM cell (102) comprises: a third MOS transistor (112), having a gate node, a source node, and a drain node, wherein the drain node of the third MOS transistor (112) is electrically connected to the source node of the first MOS transistor (114).
  2. The ROM (100) of claim 1, characterized in that the first data value is a data value of 0, the source node of the first MOS transistor (114) is electrically connected to a reference voltage, and the drain node of the first MOS transistor (114) is electrically connected to a bit line; or wherein the first data value is a data value of 0, the drain node of the first MOS transistor (114) is electrically connected to a reference voltage, and the source node of the first MOS transistor (114) is electrically connected to a bit line.
  3. The ROM (100) of any one of claims 1 or 2, characterized in that the first data value is a data value of 1, both of the source node and the drain node of the first MOS transistor (114) are electrically connected to a bit line; or the first data value is a data value of 1, both of the source node and the drain node of the first MOS transistor (114) are electrically connected to a reference voltage; or the first data value is a data value of 1, one of the source node and the drain node of the first MOS transistor (114) is floating; or the first data value is a data value of 1, both of the source node and the drain node of the first MOS transistor (114) are floating.
  4. The ROM (100) of any one of claims 1 to 3, characterized in that the ROM (100) further comprises: a plurality of dummy cells (812, 814, 816, 818), wherein a metal trace (802, 804) is routed above the plurality of dummy cells (812, 814, 816, 818), and a reference voltage is delivered through the metal trace.
  5. The ROM (100) of any one of claims 1 to 4, characterized in that the ROM (100) further comprises: a first bit line (BLO-A, BL1-A); and a second bit line (BLO-B, BL1-B); wherein the drain node of the first MOS transistor is electrically connected to one of the first bit line (BLO-A, BL1-A) and the second bit line (BLO-B, BL1-B), and the source node of the first MOS transistor is electrically connected to one of the first bit line (BLO-A, BL1-A) and the second bit line (BLO-B, BL1-B); and the first data value is read from the first ROM cell through the first bit line (BLO-A, BL1-A) and the second bit line (BLO-B, BL1-B).
  6. The ROM (100) of claim 5, characterized in that the first data value is a data value of 0, the drain node is electrically connected to one of the first bit line (BLO-A, BL1-A) and the second bit line (BLO-B, BL1-B), and the source node is electrically connected to another of the first bit line (BLO-A, BL1-A) and the second bit line (BLO-B, BL1-B); or the first data value is a data value of 1, both of the drain node and the source node are electrically connected to a same bit line of the first bit line (BLO-A, BL1-A) and the second bit line (BLO-B, BL1-B).
  7. A method for writing a read-only memory, ROM, code into a ROM (100), characterized by : determining a VIA layer design of the ROM (100) according to the ROM code, comprising: determining a VIA layer design of a second ROM cell (106) according to a VIA layer design of a first ROM cell (104) and a data value to be stored in the second ROM cell (106), wherein the ROM (100) has no isolation devices inserted into at least three contiguous ROM cells that are connected to different word lines, and the first ROM cell (104) and the second ROM cell (106) are adjacent ROM cells; and writing the ROM code into the ROM (100) by manufacturing vias of the ROM (100) according to the VIA layer design of the ROM (100).
  8. The method of claim 7, characterized in that the first ROM cell (104) comprises: a first meta-oxide-semiconductor, MOS, transistor (114), having a gate node, a source node, and a drain node; the second ROM cell (106) comprises: a second MOS transistor (116), having a gate node, a source node, and a drain node; wherein a same VIA setting is shared between the drain node of the first MOS transistor (114) and the source node of the second MOS transistor (116).
  9. The method of any one of claims 7 or 8, characterized in that a VIA layer design of the first ROM cell (104) defines that the drain node of the first MOS transistor (114) is electrically connected to a bit line, the data value to be stored in the second ROM cell (106) is a data value of 1, and a VIA layer design of the second ROM cell (106) defines that the drain node of the second MOS transistor (116) is electrically connected to the bit line.
  10. The method of any one of claims 7 to 9, characterized in that a VIA layer design of the first ROM cell (104) defines that the drain node of the first MOS transistor (114) is electrically connected to a bit line, the data value to be stored in the second ROM cell (106) is a data value of 0, and a VIA layer design of the second ROM cell (106) defines that the drain node of the second MOS transistor (116) is electrically connected to a reference voltage.
  11. The method of any one of claims 7 to 10, characterized in that a VIA layer design of the first ROM cell (104) defines that the drain node of the first MOS transistor (114) is electrically connected to a reference voltage, the data value to be stored in the second ROM cell (106) is a data value of 1, and a VIA layer design of the second ROM cell (106) defines that the drain node of the second MOS transistor (116) is electrically connected to the reference voltage.
  12. The method of any one of claims 7 to 11, characterized in that a VIA layer design of the first ROM cell (104) defines that the drain node of the first MOS transistor (114) is electrically connected to a reference voltage, the data value to be stored in the second ROM cell (106) is a data value of 0, and a VIA layer design of the second ROM cell (106) defines that the drain node of the second MOS transistor (116) is electrically connected to a bit line.
  13. The method of any one of claims 7 to 12, characterized in that determining the VIA layer design of the ROM according to the ROM code further comprising: checking VIA layer designs of contiguous ROM cells (501, 502, 503, 504, 505, 506) to determine if there are consecutive VIA settings with a same setting, wherein the same setting defines a bit line connection; and in response to determining that there are the consecutive VIA settings with the same setting, changing at least one VIA setting of the consecutive VIA settings to a new setting, wherein the new setting removes the bit line connection.
  14. The method of claim 13, characterized in that the consecutive VIA settings are separated into a plurality of VIA setting groups (702_1, 704_1) by the at least one VIA setting, and determining the VIA layer design of the ROM according to the ROM code further comprising: applying inversion to at least one of the plurality of VIA setting groups (702_1, 704_1), wherein the inversion changes each VIA setting from one of a reference voltage connection and the bit line connection to another of the reference voltage connection and the bit line connection.
  15. The method of any one of claims 7 to 14, characterized in that a first group of contiguous ROM cells and a second group of contiguous ROM cells is separated by one dummy cell (812, 814), and determining the VIA layer design of the ROM according to the ROM code further comprises: applying inversion to at least one of a first VIA setting group of the first group of contiguous ROM cells and a second VIA setting group of the second group of contiguous ROM cells, wherein the inversion changes each VIA setting from one of a reference voltage connection and a bit line connection to another of the reference voltage connection and the bit line connection.

Description

Field of the Invention The present invention relates to a read-only memory (ROM) design, and more particularly, to a ROM with one-transistor (1T) ROM cells and a method for writing a ROM code with bit line (BL) load optimization into the ROM. Background of the Invention A ROM is a non-volatile memory where data is fixed during the manufacturing process and is commonly used to store a boot-up code, BIOS firmware, and device driver programs in a system on a chip (SOC). However, as an SOC design becomes more complex, a larger ROM capacity is needed. Increasing the ROM storage capacity requires a larger die area, which increases the area and the power consumption of the SOC. The conventional ROM cell is formed by 1.5 transistors, where data is stored in a VD layer located in a source node of a metal-oxide-semiconductor (MOS) transistor and is isolated by an isolation device shared between two adjacent ROM cells. These dummy isolation devices in a conventional ROM waste die area and increase BL length, causing performance degradation and increased power consumption. Thus, there is a need for an innovative ROM design with no dummy isolation devices. Summary of the Invention This in mind, the present invention aims at providing a ROM with 1T ROM cells and a method for writing a ROM code with BL load optimization into the ROM. This is achieved by the ROM and the method according to independent claims. The dependent claims pertain to corresponding further developments and improvements. As will be seen more clearly from the detailed description following below, the claimed ROM includes a first ROM cell, a second ROM cell, and a third ROM cell. The first ROM cell is configured to store a first data value of a ROM code, and includes a first MOS transistor having a gate node, a source node, and a drain node. The second ROM cell is configured to store a second data value of the ROM code, and includes a second MOS transistor having a gate node, a source node, and a drain node, wherein the source node of the second MOS transistor is electrically connected to the drain node of the first MOS transistor. The third ROM cell is configured to store a third data value of the ROM code, and includes a third MOS transistor having a gate node, a source node, and a drain node, wherein the drain node of the third MOS transistor is electrically connected to the source node of the first MOS transistor. In addition, the claimed method includes: determining a VIA layer design of the ROM according to the ROM code, and writing the ROM code into the ROM by manufacturing vias of the ROM according to the VIA layer design of the ROM. The step of determining the VIA layer design of the ROM according to the ROM code includes: determining a VIA layer design of a second ROM cell according to a VIA layer design of a first ROM cell and a data value to be stored in the second ROM cell, wherein the first ROM cell and the second ROM cell are adjacent ROM cells. Brief Description of the Drawings In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof FIG. 1 is a diagram illustrating a ROM with high density 1T ROM bit-cells according to an embodiment of the present invention,FIG. 2 is a diagram illustrating an example of using the proposed 1T ROM cells to store data values,FIG. 3 is a layout diagram of 1T ROM cells shown in FIG. 2 according to an embodiment of the present invention,FIG. 4 is a diagram illustrating a 1T ROM cell code mapping scheme according to an embodiment of the present invention,FIG. 5 is a diagram illustrating a post-CVR VIA layer design of a ROM code segment according to an embodiment of the present invention,FIG. 6 is a diagram illustrating a comparison between bit line loads of the pre-CVR VIA layer design and the post-CVR VIA layer design of the same ROM code segment according to an embodiment of the present invention,FIG. 7 is a diagram illustrating operations of a DDCO scheme for additional bit line load optimization according to an embodiment of the present invention,FIG. 8 is a diagram illustrating a dummy cell insertion scheme according to an embodiment of the present invention,FIG. 9 is a diagram illustrating an example of using the proposed dual-BL 1T ROM cells to store data values,FIG. 10 is a layout diagram of dual-BL 1T ROM cells shown in FIG. 9 according to an embodiment of the present invention, andFIG. 11 is a flowchart illustrating a method of accessing (reading/writing) a ROM code of a ROM with 1T ROM cells according to an embodiment of the present invention. Detailed Description Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and i