Search

EP-4738432-A1 - SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION

EP4738432A1EP 4738432 A1EP4738432 A1EP 4738432A1EP-4738432-A1

Abstract

A semiconductor device and method of fabrication are described. The device comprising: a semiconductor RFID IC base layer (201); a passivation layer (203) located over the base layer, having a metal insert (204) within the passivation layer; a repassivation layer (205) located over the passivation layer and the metal insert; a assembly pad layer (207) located over the repassivation layer; wherein the device (250) has: a first region R1 (252) of the device, where a height of the repassivation layer is given by d 1 , and region R1 is provided with an assembly pad in the assembly pad layer (207) over the repassivation layer, that has an area A 1 ; and an nth region RN (256) of the device, where the height of the repassivation layer is given by d n , where d 1 >d n and region RN is provided with an assembly pad in the bump layer (207) over the repassivation layer, which has an area a n , where A n >A 1 .

Inventors

  • Manzi, Giuliano
  • Kolaric, Vlatko
  • EIPER, ERNST
  • ZENZ, CHRISTIAN

Assignees

  • NXP B.V.

Dates

Publication Date
20260506
Application Date
20241029

Claims (15)

  1. A semiconductor device comprising: a semiconductor RFID IC base layer (201); a passivation layer (203) located over the base layer, having a metal insert (204) within the passivation layer; a repassivation layer (205) located over the passivation layer and the metal insert; an assembly pad layer (207) located over the repassivation layer; wherein the device has: an first region R1 (252) of the device, where a height of the repassivation layer is given by d 1 , and region R1 is provided with an assembly pad in the assembly pad layer (207) over the repassivation layer, that has an area A 1 ; and an nth region Rn (256) of the device, where the height of the repassivation layer is given by d n , where d 1 >d n and region Rn is provided with an assembly pad in the assembly pad layer (207) over the repassivation layer, which has an area A n , where A n >A 1 .
  2. The semiconductor device as claimed in claim 1, wherein the semiconductor device is provided with a series of regions R1, R2... Rn, arranged in different locations on the semiconductor device, wherein the height of the repassivation layer d n decreases in each sequential region, and wherein each region is provided with an assembly pad in the assembly pad layer(207) over the repassivation layer, which has area A n ; where the area of the assembly pad (207) in each sequential region increases sequentially from A 1 to A n .
  3. The semiconductor device of any preceding claim further comprising a metallization layer (206) between the repassivation layer (205) and the assembly pad layer (207).
  4. The semiconductor device of any preceding claim , wherein the repassivation layer (205) of at least one of the regions R1 to RN is provided with a series of one or more cavities (401) connected with one of the assembly pad layer (207) or the repassivation layer (205) of the specific region.
  5. The semiconductor device of claim 4 wherein the series of cavities (401) in the repassivation layer (205) of at least one of regions R1 to RN is located underneath the antenna pad (304).
  6. The semiconductor device as claimed in claim 4 or claim 5 wherein the cavities (401) in the repassivation layer (205) in each of the regions R1 to Rn, have a depth that is different for each of the regions R1,... Rn.
  7. The semiconductor device as claimed in claim 6 wherein the depth for each of the cavities (401) in successive regions is less than the depth of the cavities in the previous region.
  8. The semiconductor device of any preceding claim wherein the assembly pad of at least one of the regions R1 to RN is provided with one or more slots (701) connected with located within at least one of the assembly pad or the repassivation layer (205) of the specific region.
  9. The semiconductor device of claim 8 wherein the one or more slots (701) in the repassivation layer of at least one of regions R1 to Rn is located underneath the. antenna pads
  10. The semiconductor device of claim 9 wherein the one or more slots (701) in the repassivation layer in each of the regions R1 to Rn, have a depth that is different for each of the regions R1,...Rn.
  11. The semiconductor device of claim 10 wherein the depth for each of the one or more slots (701) in successive regions R1,..Rn is less than the depth of the slots in the previous region.
  12. The semiconductor device as claimed in any of claims 3 to 11 wherein the metallization layer (206) is at least partially removed from the cavities (401) or the slots (701) in the repassivation layer (205).
  13. The semiconductor device as claimed in any of claims 3 to 11 wherein one or more of the cavities (401) or slots (701) are filled with adhesive.
  14. The semiconductor device as claimed in any preceding claim wherein the assembly pad is an electroplated metal pad.
  15. A method of forming a semiconductor device comprising the steps of: providing a semiconductor RFID base layer (201); having a series of regions R1,...Rn, where R1 is a first region on a wafer, and Rn is the nth region on a wafer (250), providing at least one metal insert (204) on an interior part of a top surface of the semiconductor RFID base layer; providing a first passivation layer (203) on the top surface of the semiconductor RFID base layer, around the at least one metal insert; providing a repassivation layer (205) over a top surface of the first passivation layer, and a top surface of an outer edge of the metal insert; depositing an under-bump metallization layer (206) on an exposed top surface of the metal insert, and inner sidewalls of the repassivation layer and a top surface of the repassivation layer; wherein a height of the repassivation layer in R1 is given by d 1 , and region R1 is provided with an assembly pad (207) over the repassivation layer (205), that has an area A 1 ; and wherein the height of the repassivation layer (205) in region Rn is given by d n , where d 1 >d n and region RN is provided with an assembly pad (207) over the repassivation layer (205), which has an area a n , where A n >A 1 .

Description

Technical Field The technical field relates to the fabrication of a semiconductor device with improved radio frequency (RF) input reactive impedance variation over the semiconductor wafer. The technical field is applicable to, but not limited to, a Radio-Frequency Identification (RFID) Integrated Circuit (IC) which enables automatic identification and tracking, as well as sensors such as capacitance sensors, temperature sensors and humidity sensors. Background Due to the intrinsic effects of the wafer manufacturing process, the radio frequency (RF) input impedance of a Radio-Frequency Identification Integrated Circuit (RFID IC) may vary over a wafer. This is illustrated in FIG. 1, where a semiconductor wafer 100, with RFID semiconductor ICs 101 is shown alongside graph 102, showing the variation in capacitance across the wafer. As shown, there is significant variation in capacitance across the wafer 100. This variation of input impedance has a strong impact on overall RFID label performances (for example, a variation of 5% in the input impedance may have up to 3dB degradation in performances of the final RFID assembly). FIG. 2 is an illustration of the steps in a known bumping process. The process shown is a modification of a standard repassivation and re-distribution process and is generally carried out on a thick wafer. As shown, at step 220 a thick unsawn wafer is provided, typically a silicon substrate, with a bond pad 204, and passivation layer 203 on top semiconductor die 201. Step 222 is provision of the Polyimide layer (PI) coating, and this is followed by step 224, PI exposure. This is followed by step 226, developing the PI layer. After this is step 228, hard cure of the PI layer. This is followed by step 230, seed layer sputter, and then step 232, provision of photoresist (PR) coating. This is followed by step 234, PR exposure, step 236, PR developing, step 238 Galvano plating, step 240 PR stripping, and step 242 seed layer etching, Au etching and TiW etching. The result of these process steps is a thick unsawn wafer 244 with repassivation layer and large area pads. Typically, a plurality of RFID semiconductor ICs will be processed on a single wafer. The bump process is processing the Repassivation and redistribution layer, processed on a wafer. The pre-assembly stage includes electrical Testing of the wafers, thinning, mounting on Film Frame Carriers (FFC), dicing in to singulated ICs. The final assembly step of the RFID semiconductor is assembly with an antenna by Flip Chip Thermocompression process. Referring now to FIG. 3, this shows a partial cross-sectional view of the RFID semiconductor die 201, with extra fabrication components that have been placed on the wafer during the fabrication process of Figure 2. Above the top surface metal layer of the die 201 is passivation layer 203, this is preferably a SiO or, SiN layer. A metallic bond pad, with a typical size of 50×50µm is shown at 204, preferably this is an aluminium bond pad. A repassivation layer is shown at 205, this is preferably, a Polyimide layer (PI) or a Polybenzoxazoles (PBO) layer, with a typical thickness of 3-20µm. Feature 206 is an Under Bump Metallization, formed from sputtered TiW/ Au flash with a thickness of 100nm-1000nm. This feature connects the Bond pads, acts as a barrier layer, increases adhesion, and is used as seed layer for subsequent Au-deposition by electroplating. Feature 207 are large connection Pads, typically these are electroplated Au-pads ("bump") of 1-10µm Au for connection with RFID antenna (200×200µm) depending on IC size). Aalternatively the bumps may be formed of Cu for example. The inventors have recognised and appreciated that a solution that enables better control of, or reduction in, the variation of the impedance over the wafer will bring a final RFID assembly having a limited variation in performance and better manufacturing yield. Accordingly, there is a need for an improved semiconductor die and method of fabrication. Summary of the invention The present invention provides a semiconductor die and method of fabrication of the semiconductor die, as described in the accompanying claims. Specific embodiments are set forth in the dependent claims. These and other aspects will be apparent from and elucidated with reference to the embodiments described hereinafter. Brief description of the drawings Further details, aspects and embodiments will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates a plan view of a prior art semiconductor wafer and a graph showing how the capacitance / impedance changes across the wafer;FIG. 2 illustrates a prior art bumping process;FIG. 3 shows a cross section of a partial semiconductor die according to the prior art;FIG. 4(