EP-4738437-A1 - SUBSTRATE PACKAGE

Abstract

There is provided a substrate package and method of manufacturing thereof. The substrate package comprises a carrier; a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier; a non-conductive first barrier wall extending from the second major surface towards the carrier, the first barrier wall defining first and second regions of the substrate package; and a ball grid array comprising a plurality of solder balls located between the substrate and the carrier, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region.

Inventors

• LIU, Huanhuan
• Sun, Yung-Ching
• ZANG, Yuan
• LEE, YIT MENG

Assignees

• NXP USA, Inc.

Dates

Publication Date

20260506

Application Date

20250108

Claims (15)

1. A substrate package comprising: a carrier; a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier; a non-conductive first barrier wall extending from the second major surface towards the carrier, the first barrier wall defining first and second regions of the substrate package; and a ball grid array comprising a plurality of solder balls located between the substrate and the carrier, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region.
2. The substrate package of claim 1, wherein the first barrier wall extends from the second major surface to the carrier.
3. The substrate package of claim 1 or claim 2, wherein the first barrier wall extends across a complete width of the substrate package.
4. The substrate package of any preceding claim, further comprising non-conductive second and third barrier walls located at opposing ends of the substrate package to further define the first and second regions.
5. The substrate package of claim 4, wherein the second and third barrier wall extend from the second major surface to the carrier.
6. The substrate package of claim 4 or claim 5, wherein the second and third barrier walls are perpendicular to the first barrier wall.
7. The substrate package of any of claims 4 to 6, wherein the second and third barrier walls extend across a complete length of the substrate package.
8. The substrate package of any preceding claim, wherein the first region corresponds to a first voltage domain and wherein the second region corresponds to a second voltage domain.
9. The substrate package of any preceding claim, wherein the first region has a larger surface area than the second region.
10. The substrate package of any preceding claim, wherein the first barrier wall comprises a plurality of walls.
11. The substrate package of any preceding claim, wherein the barrier wall(s) has a thickness that is greater than a diameter of the solder balls.
12. The substrate package of any preceding claim, wherein the barrier wall(s) forms a seal between the first and carriers.
13. The substrate package of any preceding claim, wherein the barrier wall(s) is made from an epoxy material.
14. A method of manufacturing a substrate package, the method comprising: forming a ball grid array comprising a plurality of solder balls distributed on a substrate in a first region and a second region, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region; forming a non-conductive first barrier wall on the substrate between the first and second regions; and mounting the substrate comprising the solder balls and the first barrier wall to a carrier to form the substrate package.
15. The method of claim 14, further comprising forming non-conductive second and third barrier walls perpendicular to the first barrier wall and located at two opposite sides of the substrate package.

Description

FIELD The present disclosure relates to a substrate package. In particular, the present disclosure relates to a substrate package comprising a ball grid array with electrical isolation and a method of fabrication thereof. BACKGROUND Ball grid arrays, BGA, are a type of surface-mount packaging used in integrated circuits. To ensure safety and reliability, clearance and creepage distances need to be considered in prevention of electrical breakdowns and short circuiting, for example. Clearance distance refers to the shortest distance through air between two conductive parts or between a conductive part and the grounded surface of the equipment. It is a measure of the insulation's ability to withstand electrical stress without breaking down. Creepage distance is the shortest path along the surface of an insulating material between two conductive parts or between a conductive part and the grounded surface of the equipment. This distance helps to prevent surface leakage currents occurring due to contamination, moisture, or other environmental factors. To comply with requirements of clearance and creepage distance, package size can become large, especially in high voltage domains. Depopulating BGA balls can help towards managing creepage, however, imbalances in distribution can cause further issues with ball level reliability. SUMMARY According to a first aspect, there is provided a substrate package. The substrate package comprises a carrier; a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier; a non-conductive first barrier wall extending from the second major surface towards the carrier, the first barrier wall defining first and second regions of the substrate package; and a ball grid array comprising a plurality of solder balls located between the substrate and the carrier, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region. In some embodiments, the first barrier wall may extend from the second major surface to the carrier. The carrier includes a printed circuit board, PCB, comprising a soldermask layer such that the first barrier wall extends a complete distance between the substrate and the carrier. In some embodiments, the first barrier wall extends across a complete width of the substrate package. For example, to completely isolate the first and second regions along the width of the substrate package. In some embodiments, the substrate package may further comprise non-conductive second and third barrier walls located at opposing ends of the substrate package to further define the first and second regions. The second and third barrier walls are located at or close to the periphery of the substrate package. In some embodiments, the second and third barrier wall may extend from the second major surface to the carrier. In some embodiments, the second and third barrier walls may be perpendicular to the first barrier wall. In some embodiments, the second and third barrier walls may extend across a complete length of the substrate package. The length of the substrate package and the width of the substrate package may be similar in dimension. In some embodiments, the first region corresponds to a first voltage domain and the second region corresponds to a second voltage domain. In some embodiments, the first region has a larger surface area than the second region. In some embodiments, the first barrier wall comprises a plurality of walls. In some embodiments, the barrier wall (e.g. the first barrier wall or the first, second and third barrier walls) has a thickness that is greater than a diameter of the solder balls. In some embodiments, the barrier wall (e.g. the first barrier wall or the first, second and third barrier walls) forms a seal between the substrate and the carrier. In some embodiments, wherein the barrier wall (e.g. the first barrier wall or the first, second and third barrier walls) is made from an epoxy material. According to a second aspect, there is provided a method of manufacturing a substrate package. The method comprises forming a ball grid array comprising a plurality of solder balls distributed on a substrate in a first region and a second region, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region; forming a non-conductive first barrier wall on the substrate between the first and second regions; and mounting the substrate comprising the solder balls and the first barrier wall to a carrier to form the substrate package. In some embodiments, the method further comprises forming non-conductive second and third barrier walls perpendicular to the first barrier wall and located at two opposite sides of the substrate package. In some embodiments, forming the barrier wall further comprises applying adhesive to a top surface of th