EP-4738438-A1 - SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE INTERCONNECTION AND METHOD OF FORMING THE SAME

Abstract

An IC stack includes: semiconductor structures horizontally separate with each other, each semiconductor structure having a top surface, a bottom surface opposite the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; the area of the bottom or top surface larger than that of any sidewall; and a laterally extending RDL structure covering the first sidewall of each semiconductor structure. A first semiconductor structure of the semiconductor structures comprises a first IC structure and a first neighboring structure separate from the first IC structure, the first IC structure and the first neighboring structure arranged along the first sidewall of the first semiconductor structure. The laterally extending RDL structure comprises bonding pads arranged along the first sidewall of the first semiconductor structure, the bonding pads over an edge of the first IC structure and an edge of the first neighboring structure.

Inventors

• TONG, HO-MING
• LU, CHAO-CHUN

Assignees

• nD-HI Technologies Lab, Inc.
• Etron Technology, Inc.

Dates

Publication Date

20260506

Application Date

20250221

Claims (10)

1. An IC stack comprising: a plurality of semiconductor structures horizontally separate with each other, wherein each semiconductor structure has a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall; wherein the area of the bottom surface or the top surface is larger than that of any sidewall; and a laterally extending RDL structure covering the first sidewall of each semiconductor structure; wherein a first semiconductor structure of the plurality of semiconductor structures comprises a first integrated circuit (IC) structure and a first neighboring structure physically separate from the first IC structure, wherein the first IC structure and the first neighboring structure are arranged along the first sidewall of the first semiconductor structure; wherein the laterally extending RDL structure comprises a first plurality of bonding pads arranged along the first sidewall of the first semiconductor structure, wherein the first plurality of bonding pads are over an edge of the first integrated circuit (IC) structure and over an edge of the first neighboring structure.
2. The IC stack of claim 1, wherein the number of the first plurality of bonding pads is more than 1300 to 1500.
3. The IC stack of claim 1, wherein the first neighboring structure comprises another IC structure, an interconnect spacer, a molding compound layer, or a high thermal conductivity layer with the thermal conductivity higher than that of Si.
4. The IC stack of claim 3, wherein the first IC structure or the another IC structure includes a set of through-semiconductor vias (TSVs) electrically coupled to a subset of the first plurality of bonding pads.
5. The IC stack of claim 3, wherein the molding compound layer comprises a set of through-molding vias (TMVs) electrically coupled to a subset of the first plurality of bounding pads.
6. The IC stack of claim 3, wherein the interconnect spacer is a semiconductor interposer with a set of through-semiconductor vias (TSVs) electrically coupled to a subset of the first plurality of bonding pads.
7. The IC stack of claim 1, further comprising a high thermal conductivity structure next to the first semiconductor structure, wherein the thermal conductivity of the high thermal conductivity structure is higher than that of Si.
8. The IC stack of claim 1, wherein each first IC structure comprises a DRAM semiconductor die, and the IC stack is an HBM compatible structure.
9. The IC stack of claim 8, further comprising a logic control chip under and electrically connected to the laterally extending RDL structure of the IC stack.
10. The IC stack of claim 1, further comprising a laterally extending thermal conductivity layer covering each second sidewall of the plurality of semiconductor structures, wherein the laterally extending RDL structure is opposite to the laterally extending thermal conductivity layer, and the thermal conductivity of the laterally extending thermal conductivity layer is higher than that of Si.

Description

FIELD This disclosure relates in general to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device with side edge interconnection and a method of forming the same. BACKGROUND Tremendous progress has been made in two dimensional (2D) geometrical scaling of conventional transistors due to the great feats of engineering and material science involving extremely complex multiple-step lithographic patterning, new strain enhancing materials and metal oxide gate. However, 2D device scaling is losing momentum as the abovementioned techniques approach their practical limits. Three-dimensional integrated circuit (3D IC) integration which represents a radical departure from the traditional 2D IC integration has been recognized as a next-generation semiconductor technology to simultaneously achieve high performance, low power consumption, small physical size and high integration density. The 3D ICs provide a path to continually meet performance and cost demands of next generation devices while still permitting more relaxed gate lengths with less process complexity for high-end applications such as high-performance computing (HPC), data centers and artificial intelligence (AI). 3D IC integration can proceed via monolithic integration, and/orvertical integration of disparate dies. 3D monolithic integration involves typically vertical integration of multiple active silicon layers with vertical interconnects between the layers. Recently, a "cache-on-central processing unit (CPU)" 3D IC structure has been demonstrated and commercialized using copper hybrid bonding. Today, high-bandwidth-memory (HBM) dynamic random-access memory (DRAM) stacks, each of which created by vertically integrating a number of DRAM dies on a control IC, represent the highest volume commercial 3D ICs today. These HBM DRAM stacks are typically mounted side-by-side with a processor IC on a silicon interposer in 2.5D IC packaging (FIG. 1A) for high-end applications such as HPC, data centers and AI. A 2.5D IC typically contains through- silicon vias (TSVs) in active dies such as DRAM and control ICs, and in the silicon interposer which can be passive or active. A 2.5D IC can also contain redistribution layers (RDLs) in the interposer and active dies. Take ChatGPT for instance, it is powered by nVidia's H100 GPU in 2.5D IC configuration. Going forward, 3D ICs can enable memory on memory, memory over logic, and logic over logic structures using interconnect technologies including TSVs, RDLs containing interconnect wiring and micro-vias, flip chip bonding based on copper pillar micro-bumps or solder bumps, as well as the newly emerged technique of copper hybrid bonding. 3D ICs created by monolithic integration and/or heterogeneous integration allow for vertical stacking of heterogeneous dies and/or active silicon layers from different manufacturing processes and nodes, chip/chiplet reuse, and chiplets-in-SiP (system-in-a-package). Ultimately, 3D IC integration will enable stacking of HBM DRAM stacks on processors to greatly shorten the time of data transfer between DRAM dies and the processor and greatly reduce the peak compute memory bandwidth gap. 3D ICs are ideal for applications that require integration of more transistors in a given footprint (such as mobile system-on-chip, SoC) or for applications already pushing the capability limit of a single die at the most-advanced node, such as HPC, data centers, AI /machine learning, 5G/6G networks, graphics, smartphones/wearables, automotive and others that demand ultra-high-performance, higher-power-efficiency devices. These devices include CPU, GPU (graphics processing unit), FPGA (field-programmable gate array), ASIC (application-specific IC), TPU (tensor processing unit), integrated photonics, AP (application processor for cell phones), packet buffer/router devices, and the like. To accelerate adoption, 3D IC systems must be designed in a holistic manner via IC-package-system co-design, which involves a silicon IP, ICs/chiplets and an IC package, and addresses accompanying power and thermal challenges. In contrast to PPAC (performance, power, area and cost) optimization per square centimeter as applied in 2D packaging, IC-package-system co-design for 3D ICs aims to achieve "PPAC optimization per cubic millimeter", wherein a vertical dimension that covers ICs, interposer, IC package substrate, IC package and system printed circuit board (PCB) must all be considered in all tradeoff decisions. Today, all 3D ICs adopt packaging topologies with single-sided areal electrical interconnects, for instance, from the bottom-side of the control IC in the HBM DRAM stack, which is connected to an interposer, to DRAM dies on top of the control IC, or from the laminate substrate to the bottom side of the CPU in cache-on-CPU. In powering 3D ICs that rely on single-sided interconnects, designers must consider all stacked layers while designing a power delivery network with a