EP-4738699-A1 - TRANSFORMER-BASED BIASING CIRCUIT FOR PUSH-PULL FREQUENCY DOUBLER

Abstract

A circuit includes a frequency doubler circuit including doubler core, an input matching network, and a cancellation network between the input matching network and the doubler core. The input matching network may include an input transformer including a primary inductor, a first secondary inductor including a first terminal coupled to a first gate and a second terminal coupled to a second gate of a first transistor pair of the doubler core, and a first center tap configured to receive a first bias voltage to bias the first and second gates. The input transformer may include a second secondary inductor including a first terminal coupled to the third gate and a second terminal coupled to the fourth gate of a second transistor pair of the doubler core, and a second center tap configured to receive a second bias voltage to bias the third and fourth gates of the second transistor pair.

Inventors

• FLETE, Alexander Vincent Nicolas
• Lancon, Leo Lucas
• PRUVOST, SEBASTIEN

Assignees

• NXP B.V.

Dates

Publication Date

20260506

Application Date

20241031

Claims (11)

1. A circuit comprising: an output transformer including a primary output inductor inductively coupled to a secondary output inductor, the primary output inductor including a first terminal and a second terminal; a doubler core including a first transistor pair and a second transistor pair, the first transistor pair coupled between a first power supply terminal and a first terminal of the primary output inductor, the first transistor pair including a first gate and a second gate, the second transistor pair coupled between a second power supply terminal and the second terminal of the primary output inductor, the second transistor pair including a third gate and a fourth gate; an input matching network comprising an input transformer comprising: a primary inductor configured to receive an input signal having a first frequency; a first secondary inductor inductively coupled to the primary inductor and including a third terminal coupled to the first gate, a fourth terminal coupled to the second gate, and a first center tap configured to receive a first bias voltage to bias the first and second gates of the first transistor pair; and a second secondary inductor inductively coupled to the primary inductor and including a fifth terminal coupled to the third gate, a sixth terminal coupled to the fourth gate, and a second center tap configured to receive a second bias voltage to bias the third and fourth gates of the second transistor pair.
2. The circuit of claim 1, further comprising: a cancellation network coupled to the input matching network, the cancellation network comprising: a first capacitor including a first capacitor terminal coupled to the third terminal of the first secondary inductor and including a second capacitor terminal coupled to the fifth terminal of the second secondary inductor; and a second capacitor including a third capacitor terminal coupled to the fourth terminal of the first secondary inductor and including a fourth capacitor terminal coupled to the sixth terminal of the second secondary inductor.
3. The circuit of claim 2, wherein the cancellation network cancels a common-mode loop current, reducing sensitivity of output signals to impedances of the first and second center taps.
4. The circuit of claim 2 or 3, wherein the first and second capacitors of the cancellation network provide a current path to overcome a capacitive effect of gate-to-drain capacitances of the first and second transistor pairs.
5. The circuit of any preceding claim, wherein the first bias voltage biases the gates of the first transistor pair and the second bias voltage biases the gates of the second transistor pair.
6. The circuit of any preceding claim, wherein a second frequency of an output signal at the secondary output inductor is approximately twice the first frequency.
7. The circuit of any preceding claim, wherein the first transistor pair comprises: a first transistor including a source coupled to the first supply voltage terminal, the first gate coupled to the third terminal of the first secondary inductor, and a drain coupled to the first terminal of the primary output inductor; and a second transistor including a source coupled to the first supply voltage terminal, the second gate coupled to the fourth terminal of the first secondary inductor, and a drain coupled to the first terminal of the primary output inductor; and wherein the second transistor pair comprises: a third transistor including a source coupled to the second supply voltage terminal, the third gate coupled to the fifth terminal of the second secondary inductor, and a drain coupled to the second terminal of the primary output inductor; and a fourth transistor including a source coupled to the second supply voltage terminal, the fourth gate coupled to the sixth terminal of the second secondary inductor, and a drain coupled to the second terminal of the primary output inductor.
8. The circuit of any preceding claim, wherein the input matching network further comprises one or more third secondary inductors.
9. A method of doubling a frequency of an input signal, the method comprising: applying a first bias voltage to a first center tap of a first secondary inductor of an input transformer of an input matching network, the input transformer further including a primary inductor inductively coupled to a second secondary inductor; applying a second bias voltage to a second center tap of the second secondary inductor; receiving an input signal having a first frequency at the primary inductor; producing a first signal related to the input signal at first and second terminals of the first secondary inductor and a second signal related to the input signal at third and fourth terminals of the second secondary inductor; biasing first gates of a first transistor pair of a doubler core circuit with the first bias voltage to produce a first doubler signal and second gates of a second transistor pair of the doubler core circuit with the second bias voltage to produce a second doubler signal; applying the first doubler signal to a first terminal of a primary output inductor of an output transformer having a secondary output inductor that is inductively coupled to the primary output inductor; and applying the second doubler signal to a second terminal of the primary output inductor to provide an output signal at the secondary output inductor having a second frequency that is twice the first frequency.
10. The method of claim 9, further comprising: canceling a common-mode loop current using a cancellation network coupled to the first and second secondary inductors, wherein the cancellation network comprises: a first capacitor coupled between the first terminal of the first secondary inductor and the third terminal of the second secondary inductor; and a second capacitor coupled between the second terminal of the first secondary inductor and the fourth terminal of the second secondary inductor.
11. The method of claim 9 or 10, further comprising adjusting one or more of the first bias voltage at the first center tap or the second bias voltage at the second center tap to adjust the biasing of one or more of the first gates or the second gates.

Description

FIELD OF USE The present disclosure generally relates to complementary metal-oxide semiconductor push-pull frequency doubler circuits, and more particularly to transformer-based biasing circuit for a push-pull frequency-doubler circuit core. BACKGROUND High frequency signal generation in millimeter-wave systems can present challenges including high phase noise, narrow-band operation, signal loss associated with signal distribution, and so on. BRIEF DESCRIPTION OF THE DRAWINGS The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures and in the detailed description indicates similar or identical items or features. FIG. 1 depicts a circuit including a transformer-based biasing circuit configured to bias transistors of a complementary metal-oxide semiconductor (CMOS) frequency doubler core, in accordance with certain embodiments.FIG. 2 depicts a graph of power gain versus the capacitance value on the center tap of the secondary inductors of the input transformer of FIG. 1 with and without capacitive common-mode cancellation, in accordance with certain embodiments.FIG. 3 depicts an image of an embodiment of the layout of the circuit of FIG. 1 on a chip, in accordance with certain embodiments.FIG. 4 depicts a flow diagram of a method of providing a frequency-doubled output using the circuit of FIG. 1, in accordance with certain embodiments. While implementations are described in this disclosure by way of example, those skilled in the art will recognize that the implementations are not limited to the examples or figures described. Rather, the figures and detailed description thereto are not intended to limit implementations to the form disclosed, but instead the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope as defined by the appended claims. The headings used in this disclosure are for organizational purposes only and are not meant to limit the scope of the description or the claims. As used throughout this application, the word "may" is used in a permissive sense (in other words, the term "may" is intended to mean "having the potential to") instead of in a mandatory sense (as in "must"). Similarly, the terms "include," "including," and "includes" mean "including, but not limited to." DETAILED DESCRIPTION A complementary metal-oxide semiconductor (CMOS) push-pull frequency doubler may include p-channel MOS field-effect transistors (PMOS) transistors and n-channel MOS field-effect transistors (NMOS) transistors configured to provide a push-pull circuit topology. The PMOS and NMOS transistors draw a relatively low current while using a relatively high voltage supply. The PMOS and NMOS transistors may need different bias voltages. Embodiments of circuits and methods are described below that may include a push-pull core with an input matching network including a transformer having a primary inductor and two secondary inductors and a capacitive common-mode cancellation network. The secondary inductors may include center taps to which different bias voltages can be applied, which may bias the NMOS and PMOS gates without using biasing resistors or series capacitors. The circuit configuration may show an improvement of approximately one to two decibels voltage swing as compared to conventional push-pull frequency doubler circuits. The circuit configuration may provide more voltage swing, no biasing resistance, and improved phase noise. The circuit configuration may use the same circuit area as a conventional transformer. Additionally, the common-mode cancellation network may render the circuit insensitive to the impedance on the center taps that provide the gate-biasing voltages. FIG. 1 depicts a circuit 100 including a transformer-based biasing circuit configured to bias transistors of a CMOS frequency doubler core, in accordance with certain embodiments. The circuit 100 may be an embodiment of a push-pull frequency doubler circuit. The circuit 100 may include an input matching network 102 configured to receive an input signal, a cancellation network 104 coupled to the input matching network 102, and a CMOS doubler core 106 coupled to the input matching network 102 via the cancellation network 104. The circuit 100 may include an output transformer including a primary inductor 110 coupled to the CMOS doubler core 106 and a secondary inductor 108 configured to provide the output signal, which may be at twice the frequency of the input signal at the input of the input matching network 102. The input matching network 102 may include a transformer including a primary inductor 112 configured to receive the input signal and is inductively coupled to both secondary inductors 114 and 116 with the same coupling coefficient k1 to produce first and second transform