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EP-4738703-A1 - A METHOD OF OPERATING A DIFFERENTIAL AMPLIFIER ARRANGEMENT, CORRESPONDING DIFFERENTIAL AMPLIFIER, INTEGRATED CIRCUIT AND SYSTEM

EP4738703A1EP 4738703 A1EP4738703 A1EP 4738703A1EP-4738703-A1

Abstract

A method of operating an amplifier circuit configured to provide an output signal at an output node based on an amplifier offset and at least one input signal received at input nodes of the amplifier circuit. The amplifier circuit further comprises at least one adjustment node configured to receive at least one adjustment signal. The method comprises, during a calibration phase of the amplifier circuit: selectively coupling the input nodes to a common calibration node and applying (110, 111) a common calibration voltage level thereto; iteratively varying (112, 114) the at least one adjustment signal based on a programmable control code (W) and applying the at least one varied adjustment signal to the at least one adjustment node; sensing the calibration output voltage produced at each iteration of the operation (112, 114) of varying the at least one adjustment signal and performing at least one comparison (116) among a i-th calibration output voltage provided by the amplifier and an (i+1)-th calibration output voltage; based at least on the comparison, checking (118) whether the (i+1)-th calibration output voltage has a polarity different from a polarity of the i-th calibration output voltage, and storing (119) the programmed value (W1) of the programmable control code (W) based on the positive result of the checking operation (118). The method further comprises, during an operating phase of the amplifier circuit: producing the at least one adjustment signal based on the stored (119) value (W1) of the control code (W) and applying the at least one produced adjustment signal to the at least one adjustment node as a result, and selectively decoupling the input nodes of the amplifier circuit from the common calibration node and applying at least one input signal to the input nodes of the amplifier circuit, providing an output signal at the output node of the amplifier circuit exempt from the amplifier offset as a result.

Inventors

  • NICOLOSI, ALESSANDRO
  • ELGANI, Alessia Maria
  • ROSSI, SANDRO

Assignees

  • STMicroelectronics International N.V.

Dates

Publication Date
20260506
Application Date
20251010

Claims (10)

  1. A method of operating an amplifier circuit (10, 12; 12') configured to provide an output signal (OUT) at an output node (128) based on an amplifier offset and at least one input signal (INP, INM) received at input nodes (120, 122) of the amplifier circuit (10, 12; 12'), wherein the amplifier circuit (10, 12; 12') further comprises at least one adjustment node (123, 125) configured to receive at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX), wherein the method comprises: during a calibration phase (T*) of the amplifier circuit (10, 12; 12'): selectively coupling (S IN ) the input nodes (120, 122) to a common calibration node and applying (110, 111) a common calibration voltage level (IN_CALIB) thereto; iteratively varying (112, 114) the at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX) based on a programmable control code (W) and applying the at least one varied adjustment signal to the at least one adjustment node (123), sensing a calibration output voltage (OUT) produced at each iteration (OUT1, OUT2) of the operation (112, 114) of varying the at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX) and performing at least one comparison (116) among a i-th calibration output voltage (OUT1) provided by the amplifier and an (i+1)-th calibration output voltage (OUT2); based at least on the comparison, checking (118) whether the (i+1)-th calibration output voltage (OUT2) has a polarity different from the polarity of the i-th calibration output voltage (OUT1), and storing (119) the programmed value (W1) of the programmable control code (W) based on the positive result of the checking operation (118); during an operating phase (T**) of the amplifier circuit (10, 12; 12'): producing the at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX) based on the stored (119) value (W1) of the control code (W) and applying the at least one produced adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX) to the at least one adjustment node (123) as a result, and selectively decoupling (S IN ) the input nodes (120, 122) of the amplifier circuit (10, 12; 12') from the common calibration node and applying at least one input signal (INP, INM) to the input nodes (120, 122) of the amplifier circuit (10, 12; 12'), providing an output signal (OUT) at the output node (128) of the amplifier circuit (10, 12; 12') exempt from the amplifier offset as a result.
  2. The method of claim 1, further comprising: during the second operating phase (T**) of the amplifier circuit (10, 12; 12'): selectively coupling the output node (128) of the amplifier circuit (10, 12; 12') to a Miller compensating stage (R M , C M ); selectively coupling (CALIB, S A ) a first amplifier input node (120) of the amplifier circuit (10, 12; 12') to a first input node (INP) to receive a first input signal (INP) therefrom; selectively coupling (OPAMP_CLOSED, S B , Sc) a second amplifier input node (122) to a second input node (OUT, INM) comprising either a second node (INM) to receive a second input signal therefrom or the output node (128) of the operational amplifier (12) to form a closed loop therewith.
  3. The method of claim 1 or claim 2, comprising: triggering the start of the calibration phase of the amplifier circuit (10, 12; 12') in response to asserting (14) a calibration control signal (CALIB) with a first logic value; and/or de-asserting a calibration control signal (D_MUX_OUT) with a second logic value, thereby detecting the end of the calibration phase and the start of the operating phase of the amplifier circuit (10, 12; 12').
  4. The method of any one of the previous claims, wherein performing said at least one comparison (116) among the i-th output voltage (OUT1) and the (i+1)-th output voltage (OUT2) during the calibration phase (T*) of the amplifier circuit (10, 12; 12') comprises: selectively coupling (110; S) the output node (128) of the amplifier circuit (10, 12; 12') to a sensing node (140) of a digital circuit block (14); providing (16) a clock signal (CK) to the digital circuit block (14); via said digital circuit block (14), performing analog-to-digital, ADC conversion (127) of the i-th output signal (OUT1) and the (i+1)-th output signal (OUT2), obtaining a i-th digital output (OUT_DIG_OMPAMP) and a (i+1)-th digital output as a result; and performing at least one comparison between the i-th digital output (OUT_DIG_OMPAMP) and the (i+1)-th digital output, in response to a negative result of the checking operation (118), varying the i-th control code value (W1) by a programmable amount (OF).
  5. The method of claim 4, wherein providing said clock signal (CK) to the digital circuit block (14) comprises selectively decoupling said Miller compensating stage (R M , C M ) from the output node (128) of the amplifier circuit (10, 12; 12') and coupling said Miller compensating stage (R M , C M ) to an oscillator circuit block (16) to provide said clock signal (CK) to the digital circuit block (14).
  6. The method of any one of the previous claims, wherein applying said at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX) to said at least one adjustment node (123, 125) of the amplifier circuit (10, 12; 12') comprises providing a digital counter and driving a variable current generator (20) to generate a current signal (I_OFFSET) based on the digital signal (OUT_DIG_OPAMP) provided by the digital counter.
  7. The method of claim 6, comprising: monotonically increasing a digital signal (W) provided by said digital counter, providing a first ramp in which the offset current (I_OFFSET) monotonically increases, and monotonically decreasing the digital signal (W) provided by said digital counter, providing a second ramp in which the offset current (I_OFFSET) monotonically decreases; or monotonically increasing or decreasing a digital signal (W) provided by said digital counter, providing a single ramp in which the offset current (I_OFFSET) monotonically increases.
  8. A differential amplifier arrangement (10), comprising: an adjustment circuit block (20) configured to generate at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX); an operational amplifier circuit (12, 12') comprising a first (120) and a second (122) input node configured to receive at least one input signal (INP, INM; IN_CALIB), respectively; and at least one output node (128) configured to provide at least one output signal (OUT), as well as a first (Vdd) and a second (GND) supply node configured to receive a first and a second supply voltage level, respectively; at least one adjustment node (123, 125) coupled to the operational amplifier circuit (12, 12') and to the adjustment circuit block (20) to receive the at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX therefrom; wherein the operational amplifier stage (12; 12') is configured to generate the at least one output signal (OUT) based on said at least one input signal (INP, INM; IN_CALIB), the amplifier offset and at least one adjustment signal (IN_OFFSET_SX, IN_OFFSET_DX; GATE_SX, GATE_DX); control circuitry (14) configured to operate the differential amplifier arrangement (10) according to the method of any one of claims 1 to 7.
  9. An integrated circuit, comprising a differential amplifier arrangement (10) according to claim 8.
  10. A system, such as a DC-DC converter (80) or a sensor, comprising a differential amplifier arrangement (10) according to claim 8.

Description

Technical field The description relates to a method for operating differential amplifiers. One or more embodiments may relate to techniques for reducing an equivalent DC offset at input of such differential amplifiers. One or more embodiments may be applied in a DC-DC converter, for example in battery monitoring systems equipped on-board battery-powered vehicles. Technological background Differential amplifiers are well-known in the art, and may be used e.g. in sensor circuits, comparators, integrators, etc. Generally, differential amplifiers have a pair of input nodes receiving a differential input signal, and one or more output nodes (depending on whether the amplifier is in a single-ended or fully-differential configuration) configured to provide a differential output signal as an amplified version of the differential input signal. In an ideal scenario, the differential output signal is an amplified version of a difference between the input signals. Conventionally, a DC offset at the output nodes may occur, that is a non-null output signal OUT occurring at the output nodes even if no input signal IN is applied to the input nodes. For example, the DC offset may be due to an internal offset, caused by mismatch of internal circuit components. Such DC offset (which may be represented by a small continuous ΔV placed at the input nodes of the amplifier even in the absence of the input signal) may result in an amplified output voltage G*ΔV at the output nodes, where G is a DC open loop gain of the amplifier. Considering that the open loop gain G may have a relatively high value, the DC offset at the output nodes may result in a non-negligible, constant unbalance, that may affect a dynamic range performance of the amplifier, for example the output signal OUT may be constantly saturated, thus hindering the amplifier performance. For example, while in an ideal operational amplifier having a gain G, e.g., G=3, an input voltage of 1 Volt is sufficient to produce an output voltage at a level of 3 Volts, the non-ideality may result in an input voltage about 0.99 Volts being sufficient to produce the desired output, resulting in an offset about 0.01 Volt. Different solutions have been developed for the instant technical problem, for example: US 2019/363686 A1 discusses a differential amplifier including: first and second input nodes; first and second output nodes; first and second supply nodes; first and second offset compensation nodes; first and second amplifier stages configured to generate first and second output voltages at the first and second output nodes as a function of first and second input voltages of the first and second input nodes and first and second offset compensation voltages of the first and second offset compensation nodes; and a feedback circuit configured to generate the first and second offset compensation voltages as a function of the first and the second output voltages; the feedback circuit includes: a coupling circuit coupled between the first and second offset compensation nodes, wherein the coupling circuit comprises one or more passive electric components;US 2007/109043 A1 discusses a circuit for minimizing a voltage offset between inverting and non-inverting input terminals of an operational amplifier circuit, where the circuit includes a chopper circuit connected to the inverting and non-inverting input terminals of the operational amplifier circuit, the chopper circuit including: an amplifier having differential outputs; and a switching circuit for periodically reversing the input terminals to the amplifier and periodically reversing the outputs of the amplifier to provide an output signal having an offset adjustment signal to the operational amplifier circuit to adjust the offset of the operational amplifier circuit. Existing techniques envisage reducing the DC offset of the differential amplifier by acting on the amplifier itself (e.g., increasing the size of the transistors or the gain value of the differential stage). Such solutions present the drawback of an increased power consumption. Alternatively, either static compensation techniques (SCT) or dynamic compensation techniques (DCT) can be used. SCT techniques envisage applying a correction factor to the amplifier, where the correction factor is based on measurements performed while the application is not running (e.g., during manufacturing). The measured correction factor can be stored (e.g., in a non-volatile memory, NVM) and applied during operation of the amplifier. DCT techniques envisage dynamic removal of the offset from the output voltage and can be based on: i) sampling the offset and its subtraction from the output (currently referred to as auto-zeroing);ii) modulation of the offset to high frequency (e.g., through chopping at a frequency higher than the input signal frequency) and elimination from the output voltage by a low-pass or notch filter. Both solutions involve the presence of a continuous clock (plus a storag