EP-4738709-A1 - PHASE-LOCKED LOOP CIRCUIT, PHASE-LOCKING METHOD, AND FREQUENCY SYNTHESIZER

EP4738709A1EP 4738709 A1EP4738709 A1EP 4738709A1EP-4738709-A1

Abstract

A phase-locked loop circuit, a phase-locking method, and a frequency synthesizer are provided. The phase-locked loop circuit employs phase-rolling clock signal generator component to perform integer frequency division on multiple oscillation clock signals with uniformly varying phases to obtain multiple feedback clock signals with uniformly varying phases; and according to a preset clock cycle, select feedback clock signals with corresponding phase sequences from the multiple feedback clock signals with uniformly varying phases for concatenation, thereby generating the phase-rolling clock signal. This architecture enables fractional-N frequency division phase-locked loop operation. Compared with conventional fractional-N frequency division phase-locked loop implementations using sigma-delta modulator (SDM) circuits, the proposed solution reduces circuit area and power consumption while improving phase-locked loop performance.

Inventors

ZOU, WEIHUA
ZHANG, YAOZHONG

Assignees

Amlogic (Shanghai) Co., Ltd.

Dates

Publication Date: 20260506
Application Date: 20251029

Claims (14)

A phase-locked loop circuit, comprising: a phase detection component, configured to receive an external reference clock signal and a phase-rolling clock signal; when the phase of the phase-rolling clock signal leads the external reference clock signal, the phase detection component generates a falling control signal; and when the phase of the phase-rolling clock signal lags the external reference clock signal, the phase detection component generates a rising control signal; a loop filter component, configured to decrease a voltage value of the control voltage signal when receiving the falling control signal; and to increase the voltage value of the control voltage signal when receiving the rising control signal; a voltage-controlled oscillator component, configured to generate a plurality of oscillation clock signals with uniformly varying phases based on the voltage value of the control voltage signal; and a phase-rolling clock signal generator component, configured to perform integer frequency division on the multiple oscillation clock signals with uniformly varying phases, thereby obtaining multiple feedback clock signals with uniformly varying phases; sort the multiple feedback clock signals with uniformly varying phases according to their phase order, thereby determining their phase sequence; and according to a preset clock cycle, select feedback clock signals with corresponding phase sequences from the multiple feedback clock signals with uniformly varying phases for concatenation, thereby generating the phase-rolling clock signal.
The phase-locked loop circuit according to claim 1, wherein a target frequency of the oscillation clock signal satisfies: f VCO _ CLK = f REF _ CLK * M + X N ; wherein, f VCO_CLK represents the target frequency of the oscillation clock signal, f REF_CLK represents the frequency of the external reference clock signal, M represents the integer frequency division coefficient related to the target frequency of the oscillation clock signal, X represents the numerator of the fractional division coefficient related to the target frequency of the oscillation clock signal, X is an integer greater than zero and less than or equal to (N-1), N represents the number of multiple feedback clock signals with uniformly varying phases.
The phase-locked loop circuit according to claim 2, wherein a phase-rolling clock signal generator component includes: a frequency division processing component, configured to receive a corresponding integer frequency division coefficient and N phase-uniformly varying oscillation clock signals; and perform frequency division processing on each of the N oscillation clock signals using the integer frequency division coefficient, thereby obtaining N feedback clock signals with uniformly distributed phases; a phase alignment component, configured to sort N feedback clock signals with uniformly distributed phases according to their phase order, thereby determining phase ordinal positions of the N feedback clock signals; and to perform a NOR operation on the N feedback clock signals to generate a phase-rolling control signal; a logic control component, configured to generate a phase selection control signal according to the phase-rolling control signal, and a preset correspondence between a clock cycle of the phase-rolling clock signal and phase ordinal positions of the N phase-uniformly varying feedback clock signals; and also configured to generate a corresponding integer frequency division coefficient based on a preset condition satisfied by the clock cycle of the phase-rolling clock signal and the phase-rolling control signal; and a phase-rolling component, configured to receive the phase-rolling control signal and N phase-uniformly varying feedback clock signals; and at each clock cycle of the phase-rolling clock signal, select and concatenate feedback clock signals with corresponding phase ordinal positions from the N phase-uniformly varying feedback clock signals according to the phase selection control signal, thereby generating the phase-rolling clock signal.
The phase-locked loop circuit according to claim 3, wherein the frequency division processing component includes N frequency dividers corresponding one-to-one to the N phase-uniformly varying oscillation clock signals; the frequency dividers, configured to receive a corresponding integer frequency division coefficient and a corresponding one of N phase-uniformly varying oscillation clock signals; and perform frequency division processing on the corresponding oscillation clock signal using the integer frequency division coefficient, thereby obtaining a corresponding feedback clock signal.
The phase-locked loop circuit according to claim 4, wherein the phase alignment component includes: a sampling processing sub-component, configured to use a feedback clock signal from a frequency divider at ordinal position 0 to sample and process the feedback clock signals from the frequency dividers at ordinal positions 1 to (N-1), thereby obtaining the corresponding sampled signals; an ordering processing sub-component, configured to determine phase ordinal positions of the N phase-uniformly varying feedback clock signals based on the sampled signals; a logic operation sub-component, configured to perform a NOR logic operation on the N phase-uniformly varying feedback clock signals, thereby obtaining the phase-rolling control signal.
The phase-locked loop circuit according to claim 5, wherein the ordering processing sub-component is configured to determine phase ordinal positions of the N phase-uniformly varying feedback clock signals based on the sampled signals using the following equation: CLK _ PHASE p = FB _ CLK p + Y p + Y ≤ N − 1 FB _ CLK p + Y − N p + Y > N − 1 wherein, CLK _PHASE < p >represents the feedback clock signal whose phase order is p when the N phase-uniformly-varying feedback clock signals are sorted in ascending order of phase, FB _CLK < p+Y > represents the feedback clock signal from the frequency divider at ordinal position ( p + Y ), FB _CLK < p + Y - N > represents the feedback clock signal from the frequency divider at ordinal position ( p + Y - N ), Y represents the number of the second sampled value in the sampled signals, and Y is an integer greater than or equal to 0 and less than or equal to ( N -1) .
The phase-locked loop circuit according to claim 3, wherein the number of the second sampled value is 1.
The phase-locked loop circuit according to claim 6, wherein the logic control component includes: a first control sub-component, configured to generate a phase selection control signal according to the phase roll control signal, and a preset correspondence between the clock cycles of the phase-rolling clock signal and the phase ordinal positions of the N phase-uniformly varying feedback clock signals; a second control sub-component, configured to generate corresponding modulation values based on a preset condition satisfied by the clock cycle of the phase-rolling clock signal and the phase-rolling control signal; and an adder operation sub-component, configured to calculate the sum of the corresponding modulation value and the integer division coefficient related to the target frequency of the oscillation clock signal, thereby obtaining the corresponding integer frequency division coefficient.
The phase-locked loop circuit according to claim 8, wherein the first control sub-component, configured to obtain the phase order of the feedback clock signals output by the phase-rolling component in each clock cycle of the phase roll clock signal, based on the preset correspondence between the clock cycles of the phase roll clock signal and the phase order of the N phase-uniformly varying feedback clock signals; and output the phase order of the corresponding feedback clock signal as the phase selection control signal during the preset clock cycle when the phase roll control signal has a first logic level; wherein a preset correspondence between the clock cycles of the phase roll clock signal and the phase order of the N phase-uniformly varying feedback clock signals satisfies: k = l * X l * X − j l * N 0 ≤ l * X < N l * X ≥ N ; and j l = 0 j l − 1 j l − 1 + 1 l = 0 0 ≤ l * X < j l − 1 * N l * X ≥ j l − 1 * N ; wherein, k represents the phase order of the feedback clock signal output by the phase-rolling component during the l -th clock cycle of the phase roll clock signal, j l represents the carry count value of the integer frequency division coefficient related to the target frequency of the oscillation clock signal during the l -th clock cycle of the phase roll clock signal, j l- 1 represents the carry count value of the integer frequency division coefficient M related to the target frequency of the oscillation clock signal during the ( l -1) -th clock cycle of the phase roll clock signal.
The phase-locked loop circuit according to claim 8, wherein the second control sub-component, configured to generate a first modulation value when the phase-rolling control signal is at a first logic level and the clock cycle of the phase-rolling clock signal satisfies preset condition 0 ≤ i * X < N ; and to generate a second modulation value when the phase-rolling control signal is at a first logic level and the clock cycle of the phase-rolling clock signal satisfies preset condition l* X - j l -1 * N ≥ N ; the adder operation sub-component, configured to calculate a sum of the integer frequency division coefficient M related to the target frequency of the oscillator clock signal and the first modulation value as a corresponding integer frequency division coefficient, upon receiving the first modulation value; and to calculate a sum of the integer frequency division coefficient M related to the target frequency of the oscillator clock signal and the second modulation value as a corresponding integer frequency division coefficient, upon receiving the second modulation value.
The phase-locked loop circuit according to claim 10, wherein the first modulation value is 0, and the second modulation value is 1.
The phase-locked loop circuit according to claim 10, wherein the first logic level is defined as a low level.
A phase-locking method, comprising: using a phase detection component to receive an external reference clock signal and a phase-rolling clock signal; when the phase of the phase-rolling clock signal leads the external reference clock signal, the phase detection component generates a falling control signal; and when the phase of the phase-rolling clock signal lags the external reference clock signal, the phase detection component generates a rising control signal; using a loop filter component to decrease a voltage value of the control voltage signal when receiving the falling control signal; and to increases the voltage value of the control voltage signal when receiving the rising control signal; using a voltage-controlled oscillator component to generate a plurality of oscillation clock signals with uniformly varying phases based on the voltage value of the control voltage signal; and using a phase-rolling clock signal generator component to perform integer frequency division on the multiple oscillation clock signals with uniformly varying phases, thereby obtaining multiple feedback clock signals with uniformly varying phases; to sort the multiple feedback clock signals with uniformly varying phases according to their phase order, thereby determining their phase sequence; and according to a preset clock cycle, select feedback clock signals with corresponding phase sequences from the multiple feedback clock signals with uniformly varying phases for concatenation, thereby generating the phase-rolling clock signal.
A frequency synthesizer, comprising the phase-locked loop circuit according to any one of claims 1 to 12.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 202411534796.9, filed on Oct.30, 2024, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD Embodiments of the present disclosure relate to the field of circuit technology, and in particular to a phase-locked loop circuit, a phase-locking method, and a frequency synthesizer. BACKGROUND In the field of wireless communication, frequency synthesizers based on phase-locked loop (PLL) structures are widely used to generate oscillation signals. Among them, the fractional-N frequency division phase-locked loop (PLL) circuit are applied in many clocks due to their flexible frequency planning. The digital Sigma-Delta Modulator (SDM) is one of the main components of the fractional-N frequency division phase-locked loop (PLL) circuit. The SDM circuit provides flexibility to the PLL with fractional multiplication factors by jittering the division value of the PLL feedback divider, and has the advantage of noise shaping. However, the SDM circuit has issues with large circuit area occupation and with high power consumption, which impact the area and power consumption of the fractional-N frequency division PLL circuits. SUMMARY A problem resolved by some embodiments of the present disclosure is to provide a phase-locked loop circuit, a phase-locking method, and a frequency synthesizer, which achieve a fractional-N phase-locked loop while saving the area and power consumption of the phase-locked loop circuit. To resolve the above problem, some embodiments of the present disclosure provide a phase-locked loop circuit, including: a phase detection component, configured to receive an external reference clock signal and a phase-rolling clock signal; when the phase of the phase-rolling clock signal leads the external reference clock signal, the phase detection component generates a falling control signal; and when the phase of the phase-rolling clock signal lags the external reference clock signal, the phase detection component generates a rising control signal; a loop filter component, configured to decrease a voltage value of the control voltage signal when receiving the falling control signal; and to increase the voltage value of the control voltage signal when receiving the rising control signal; a voltage-controlled oscillator component, configured to generate a plurality of oscillation clock signals with uniformly varying phases based on the voltage value of the control voltage signal; and a phase-rolling clock signal generator component, configured to perform integer frequency division on the multiple oscillation clock signals with uniformly varying phases, thereby obtaining multiple feedback clock signals with uniformly varying phases; sort the multiple feedback clock signals with uniformly varying phases according to their phase order, thereby determining their phase sequence; and according to a preset clock cycle, select feedback clock signals with corresponding phase sequences from the multiple feedback clock signals with uniformly varying phases for concatenation, thereby generating the phase-rolling clock signal. Optionally, a target frequency of the oscillation clock signal satisfies: fVCO_CLK=fREF_CLK*M+XN; wherein, fVCO_CLK represents the target frequency of the oscillation clock signal, FREF_CLK represents the frequency of the external reference clock signal, M represents the integer frequency division coefficient related to the target frequency of the oscillation clock signal, X represents the numerator of the fractional division coefficient related to the target frequency of the oscillation clock signal, and X is an integer greater than zero and less than or equal to (N-1), N represents the number of multiple feedback clock signals with uniformly varying phases. Optionally, a phase-rolling clock signal generator component includes: a frequency division processing component, configured to receive a corresponding integer frequency division coefficient and N phase-uniformly varying oscillation clock signals; and to perform frequency division processing on each of the N oscillation clock signals using the integer frequency division coefficient, thereby obtaining N feedback clock signals with uniformly distributed phases; A phase alignment component, configured to sort N feedback clock signals with uniformly distributed phases according to their phase order, thereby determining phase ordinal positions of the N feedback clock signals; and to perform a NOR operation on the N feedback clock signals to generate a phase-rolling control signal; A logic control component, configured to generate a phase selection control signal according to the phase-rolling control signal, and a preset correspondence between a clock cycle of the phase-rolling clock signal and phase ordinal positions of the N phase-uniformly varying feedback clock signals; and also configured to generate a corresponding