EP-4738736-A1 - MODEM CHIP CAPABLE OF PERFORMING CYCLIC REDUNDANCY CHECK OF A TRANSPORT BLOCK ON A CODEBLOCK BASIS USING INTERNAL MEMORY, AND SYSTEM ON CHIP INCLUDING THE MODEM CHIP

EP4738736A1EP 4738736 A1EP4738736 A1EP 4738736A1EP-4738736-A1

Abstract

A modem chip capable of receiving a codeword including a transport block including a plurality of code blocks, the modem chip including a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation including a first cyclic redundancy check and a second cyclic redundancy check with respect to the codeword, and an internal memory storing data generated during the second cyclic redundancy check. The plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and the internal memory includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence.

Inventors

BAE, JIMIN

Assignees

Samsung Electronics Co., Ltd.

Dates

Publication Date: 20260506
Application Date: 20251021

Claims (15)

A modem chip capable of receiving a codeword including a transport block including a plurality of code blocks, the modem chip comprising: a hybrid automatic repeat request, HARQ, processing circuit (110) configured to perform a HARQ-based processing operation including a first cyclic redundancy check and a second cyclic redundancy check with respect to the codeword; and an internal memory (120) configured to store data generated during the second cyclic redundancy check, wherein the HARQ processing circuit (110) comprises: a code block processing circuit (111) configured to decode the plurality of code blocks into decoded code blocks and perform the first cyclic redundancy check on each of the decoded code blocks; and a codeword processing circuit (112) configured to perform the second cyclic redundancy check on a decoded transport block by generating target blocks corresponding to the decoded code blocks based on modular arithmetic using a polynomial for the second cyclic redundancy check, the plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and the internal memory (120) includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence.
The modem chip of claim 1, wherein each of the plurality of memory elements is configured to have a capacity corresponding to a data size of a remainder generated by the modular arithmetic with respect to one target block.
The modem chip of claim 1 or claim 2, wherein a first memory management group among the plurality of memory management groups includes a first code block and a second code block arranged sequentially, a first memory element among the plurality of memory elements is allocated to the first memory management group, the codeword processing circuit (112) is further configured to access the first memory element, based on results of the first cyclic redundancy check with respect to a decoded first code block and a decoded second code block included in the decoded code blocks, and memory management information corresponding to the first memory management group, during a time period when the second cyclic redundancy check is performed, and the memory management information includes an arrangement order between the first code block and the second code block and an address of the first memory element.
The modem chip of claim 3, wherein the codeword processing circuit (112) is configured to write, to the first memory element, a first remainder generated by the modular arithmetic with respect to a first target block included in the target blocks, the first target block corresponding to the decoded first code block that has passed the first cyclic redundancy check, and to overwrite to the first memory element, a second remainder generated by the modular arithmetic with respect to a second target block included in the target blocks, the second target block corresponding to the decoded second code block that has passed the first cyclic redundancy check.
The modem chip of claim 3, wherein the codeword processing circuit (112) is further configured to write, to the first memory element, a first remainder generated by the modular arithmetic with respect to a first target block included in the target blocks, the first target block corresponding to the decoded first code block that has passed the first cyclic redundancy check, and to skip writing a second remainder generated by the modular arithmetic with respect to a second target block included in the target blocks, the second target block corresponding to the decoded second code block that has failed the first cyclic redundancy check.
The modem chip of claim 5, wherein the modem chip is configured to receive a retransmitted second code block, and the codeword processing circuit (112) is further configured to overwrite, to the first memory element, a third remainder generated by the modular arithmetic with respect to a third target block included in the target blocks, the third target block corresponding to the retransmitted second code block which passes the first cyclic redundancy check.
The modem chip of claims 3-6, further comprising a register circuit including a first register, wherein the codeword processing circuit (112) is configured to selectively access the first register based on the result of the first cyclic redundancy check and the memory management information during the time period when the second cyclic redundancy check is performed.
The modem chip of claim 7 when dependent on claim 3, wherein the codeword processing circuit (112) is configured to skip writing a first remainder generated by the modular arithmetic with respect to a first target block included in the target blocks, the first target block corresponding to the decoded first code block that has failed the first cyclic redundancy check and to write, to the first memory element, a second remainder generated by the modular arithmetic with respect to a second target block included in the target blocks, the second target block corresponding to the decoded second code block that has passed the second cyclic redundancy check.
The modem chip of claim 8, wherein the modem chip further receives a retransmitted first code block, and the codeword processing circuit (112) is further configured to write, to the first register, third intermediate data generated by the modular arithmetic with respect to a third target block included in the target blocks, the third target block corresponding to the retransmitted first code block which passes the first cyclic redundancy check.
The modem chip of any of claims 7-9, wherein a storage capacity of the internal memory (120) is greater than the register circuit.
The modem chip of any of claims 1-3 or 8-10, wherein the code block processing circuit (111) is further configured to store, in an external memory (11), a decoded second code block that has passed the first cyclic redundancy check from among the decoded code blocks, based on a decoded first code block among the decoded code blocks having failed the first cyclic redundancy check.
The modem chip of claim 11, wherein, the internal memory (120) is configured to be dedicated to the modem chip, and the external memory (11) is configured to be shared with an external device.
The modem chip of any preceding claim, wherein a memory management group unit in the plurality of memory management groups corresponds to a code block group that includes a plurality of code blocks that are retransmitted together.
The modem chip of any preceding claim, wherein the codeword processing circuit (112) is further configured to determine whether the second cyclic redundancy check has passed, based on a final remainder corresponding to the last target block among the target blocks.
The modem chip of any preceding claim, wherein the decoded code blocks include a first code block, a second code block, and a third code block sequentially processed by the code block processing circuit (111), and the target blocks comprise: a first target block including the first code block and zero bits; a second target block including the second code block, zero bits, and a first remainder obtained by dividing the first target block by the polynomial; and a third target block including the third code block, zero bits, and a second remainder obtained by dividing the second target block by the polynomial.

Description

BACKGROUND Aspects of the inventive concept relate to a modem chip forming a modem integrated circuit capable of decoding a codeword and performing a cyclic redundancy check (CRC) on the decoded codeword, and a system-on-chip including the modem integrated circuit. In a communication system, a transmission device may transmit a codeword including a transport block (e.g., payload) composed of code blocks to a reception device. The codeword may include CRC bits for performing a CRC on each code block (hereinafter, referred to as a first CRC) and transport block cyclic redundancy check (TBCRC) bits for performing a CRC with respect to a transport block (hereinafter, referred to as a second CRC). A modem of the reception device may determine whether a received codeword has been successfully decoded, by decoding the received codeword into units of decoded code blocks, performing the first CRC for each decoded code block, and performing the second CRC with respect to a decoded transport block. When a code block that has failed in the first CRC exists among the decoded code blocks, the modem may request the transmission device to retransmit a corresponding code block in units of code block groups, and decoded code blocks that have passed the first CRC may be stored in an external memory. Thereafter, the modem may read the decoded code blocks from the external memory, generate a decoded transport block by concatenating a decoding result of the retransmitted code block with the read-out decoded code blocks, and perform the second CRC on the decoded transport block. Because the external memory is also used by a processor other than the modem of the reception device, a bus connecting the external memory to each of the modem and the processor may be switched to a busy state by the processor, and thus communication through the bus between the modem and the external memory may be temporarily difficult. In addition, as the data size of the decoded code blocks stored in the external memory gradually increases with the advancement of communication technology, access to the external memory by the modem for a second CRC may increase a load on the bus and the external memory. Accordingly, a modem's second CRC on a decoded transport block may not be completed within a preset time, resulting in a degradation in the modem's performance. SUMMARY Aspects of the inventive concept provide a modem chip capable of performing a second cyclic redundancy check (CRC) based on remainders of target blocks corresponding to code blocks of a codeword and storing intermediate data generated in the second CRC in an internal memory, and a system on chip including the modem chip. Aspects of the inventive concept provide a modem chip that stores intermediate data in an internal memory, based on memory management information, to efficiently use the internal memory in the second CRC, and a system on chip including the modem chip. According to an aspect of the inventive concept, there is provided a modem chip capable of receiving a codeword including a transport block including a plurality of code blocks, the modem chip including a hybrid automatic repeat request (HARQ) processing circuit configured to perform a HARQ-based processing operation including a first cyclic redundancy check and a second cyclic redundancy check with respect to the codeword, and an internal memory storing data generated during the second cyclic redundancy check. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks into decoded code blocks and perform the first cyclic redundancy check on each of the decoded code blocks, and a codeword processing circuit configured to perform the second cyclic redundancy check on a decoded transport block by generating target blocks corresponding to the decoded code blocks based on a modular arithmetic using a polynomial for the second cyclic redundancy check. The plurality of code blocks are classified into a plurality of memory management groups each including at least two code blocks, and the internal memory includes a plurality of memory elements allocated to the plurality of memory management groups in a one-to-one correspondence. According to another aspect of the inventive concept, there is provided a modem chip capable of communicating with an external memory via a bus, the modem chip including a HARQ processing circuit configured to perform a HARQ-based processing operation including a first cyclic redundancy check and a second cyclic redundancy check with respect to a codeword including a transport block including a plurality of code blocks, and an internal memory configured to store data generated during the second cyclic redundancy check. The HARQ processing circuit includes a code block processing circuit configured to decode the plurality of code blocks into decoded code blocks, perform the first cyclic redundancy check on the decoded plurality of code blocks, and st