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EP-4738759-A1 - PHASE DETECTION DEVICE AND METHOD FOR DETECTING PHASE

EP4738759A1EP 4738759 A1EP4738759 A1EP 4738759A1EP-4738759-A1

Abstract

A receiver (RX) includes an analog front end (510) configured to receive a data input/output signal (DQ) and amplify the data input/output signal (DQ) and generate a processing signal (DQE), a time interleaved analog-to-digital converter (TI ADC 520) configured to sample the processing signal (DQE) and generate a plurality of digital data signals (DO), a Mueller-Muller phase detector (530) configured to receive the digital data signals (DO) and drive at least one of a plurality of calculators based on a transition between two digital data signals (DO), a monitoring circuit (570) configured to receive the digital data signals (DO), receive a multi-level signal (MS) transmitted from a transmitter (TX), and generate a monitoring output signal (MV) based on the digital data signals (DO) and the multi-level signal (MS), and a control logic circuit (580) configured to receive a monitoring output signal (MV) and generate a plurality of calculator selection signals (CAL_EN) for driving the calculators based on the monitoring output signal (MV).

Inventors

  • JUNG, JINOOK
  • PARK, JAEWOO
  • KWAK, Myoungbo
  • BAEK, SEUNGYEOB

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260506
Application Date
20250723

Claims (14)

  1. A receiver (RX) comprising: an analog front end circuit (510) configured to receive a data input/output signal (DQ), and amplify the data input/output signal (DQ) to generate a processing signal (DQE); a time interleaved analog-to-digital converter, TI ADC (520), configured to sample the processing signal (DQE) based on a plurality of clock signals (CK) and generate a plurality of digital data signals (DO); a Mueller-Muller phase detector (530) configured to receive the plurality of digital data signals (DO) from the TI ADC (520) and drive at least one calculator (911a) of a plurality of calculators (911a-913a) based on a transition between two digital data signals (DO) received sequentially among the plurality of digital data signals (DO); a monitoring circuit (570) configured to receive the plurality of digital data signals (DO) from the TI ADC (520), receive a multi-level signal (MS) transmitted from a transmitter (TX), and generate a monitoring output signal (MV) based on the plurality of digital data signals (DO) and the multi-level signal (MS); and a control logic circuit (580) configured to receive a monitoring output signal (MV) output from the monitoring circuit (570) and generate a plurality of calculator selection signals (CAL_EN1-CAL_EN16) that are configured to drive the plurality of calculators (911a-913a) based on the monitoring output signal (MV).
  2. The receiver (RX) of claim 1, wherein the Mueller-Muller phase detector (530) includes: a phase decision decoder circuit (910) configured to generate transition information of the two digital data signals (DO), determine phase information for clock signals (CK) used to sample the two digital data signals (DO), and output a phase decision signal (DC1-DC16) including the phase information, wherein the phase decision signal (DC1-DC16) optionally includes the transition information and/or values of the two digital data signals (DO); wherein the plurality of calculators (911a-913a) are configured to receive the phase decision signal (DC1-DC16) and generate a plurality of sampling control signals (DX1-DX16) used to control timing of the clock signals (CK) based on the phase decision signal (DC1-DC16); a plurality of switches (SX1-SX16) configured to connect the plurality of calculators (911a-913a) and a voltage source (VDD); and a plurality of multiplexers (911b-913b) configured to receive the sampling control signals (DX1-DX16) from the plurality of calculators (911a-913a) and selectively output the sampling control signals (DX1-DX16).
  3. The receiver (RX) of claim 2, wherein the phase decision decoder circuit (910) is configured to select a calculator (911a) from among the plurality of calculators (911a-913a) based on the transition information and output the phase decision signal (DC1-DC16) to the calculator (911a), and wherein the plurality of switches (SX1-SX16) are configured to be turned on or off based on the calculator selection signals (CAL_EN1-CAL_EN16).
  4. The receiver (RX) of any one of claims 1 to 3, wherein the monitoring circuit (570) is configured to: compute a signal-to-noise ratio based on signal power measured through an average square of a voltage level value of the two digital data signals (DO) or the multi-level signal (MS) and noise power including a power loss occurring in a signal transmission path, and generate the signal-to-noise ratio as the monitoring output signal (MV).
  5. The receiver (RX) of claim 4, wherein the control logic circuit (580) is configured to generate the plurality of calculator selection signals (CAL_EN1-CAL_EN16) configured to drive n calculators - a positive number where n<m - from among the plurality of calculators (911a-913a) based on the monitoring output signal (MV) that is greater than a reference value.
  6. The receiver (RX) of claim 5, wherein a group of switches (SX1-SX16) from among the plurality of switches (SX1-SX16) connected to the n calculators are configured to be turned off based on the plurality of calculator selection signals (CAL_EN1-CAL_EN16), and wherein a group of multiplexers (911b-913b) from among the plurality of multiplexers (911b-913b) that are connected to the n calculators are configured to not transfer the sampling control signals (DX1-DX16) output from the n calculators to a loop filter (540).
  7. The receiver (RX) of claim 5 or 6, wherein the control logic circuit (580) is configured to generate the plurality of calculator selection signals (CAL_EN1-CAL_EN16) configured to drive m calculators - a positive number where n<m - from among the plurality of calculators (911a-913a) based on the monitoring output signal (MV) that is less than the reference value.
  8. The receiver (RX) of claim 7, wherein another group of switches (SX1-SX16) from among the plurality of switches (SX1-SX16) connected to the m calculators are configured to be turned on based on the plurality of calculator selection signals (CAL_EN1-CAL_EN16), and wherein another group of multiplexers (911b-913b) from among the plurality of multiplexers (911b-913b) that are connected to the m calculators are configured to output sampling control signals (DX1-DX16) output from the m calculators based on the plurality of calculator selection signals (CAL_EN1-CAL_EN16).
  9. The receiver (RX) of any one of claims 1 to 3, wherein the monitoring circuit (570) is configured to: compute a bit error rate based on a total number of transmission bits of the multi-level signal (MS) transmitted from the transmitter (TX) and a number of error bits between the multi-level signal (MS) and the two digital data signals (DO), and generate the bit error rate as the monitoring output signal (MV).
  10. The receiver (RX) of claim 9, wherein the control logic circuit (580) is configured to generate the plurality of calculator selection signals (CAL_EN1-CAL_EN16) configured to drive m calculators - a positive number where n<m - from among the plurality of calculators (911a-913a) based on the monitoring output signal (MV) that is greater than a reference value.
  11. The receiver (RX) of claim 10, wherein a group of switches (SX1-SX16) from among the plurality of switches (SX1-SX16) connected to the m calculators are configured to be turned on based on the plurality of calculator selection signals (CAL_EN1-CAL_EN16), and a group of multiplexers (911b-913b) from among the plurality of multiplexers (911b-913b) connected to the m calculators are configured to output sampling control signals (DX1-DX16) output from the m calculators based on the calculator selection signals (CAL_EN1-CAL_EN16).
  12. The receiver (RX) of claim 10 or 11, wherein the control logic circuit (580) is configured generate the calculator selection signals (CAL_EN1-CAL_EN16) configured to drive n calculators - a positive number where n<m - from among the plurality of calculators (911a-913a) based on the monitoring output signal (MV) that is less than or the reference value.
  13. The receiver (RX) of claim 12, wherein another group of switches (SX1-SX16) from among the plurality of switches (SX1-SX16) connected to the n calculators are configured to be turned off by receiving the calculator selection signals (CAL_EN1-CAL_EN16), and wherein another group of multiplexers (911b-913b) from among the plurality of multiplexers (911b-913b) connected to the n calculators are configured to not transfer the sampling control signals (DX1-DX16) output from the n calculators to a loop filter (540).
  14. The receiver (RX) of any one of claims 9 to 13, wherein the monitoring output signal (MV) includes a signal representing a bit error rate that is determined based on a number of bit errors of the multi-level signal (MS) and the plurality of digital data signals (DO).

Description

BACKGROUND Although electronic devices operate internally through digital signal processing, their interfaces with external devices primarily rely on analog signal transmission. As performance of electronic devices improves, communication frequencies are becoming higher and higher, and as communication frequencies increase, an effect of jitter in signals received from external devices may become more noticeable. The effect of jitter may cause timing mismatch when a receiver samples an analog signal digitally. Timing instability may cause bit errors and sampling distortion during signal conversion. Accordingly, the integrity of the analog signal received by the receiver from the external device may be damaged. SUMMARY In general, the present disclosure is directed toward a phase detection device and a phase detection method capable of being driven by low electric power. According to some implementations, the present disclosure is directed to a phase detection device and a phase detection method capable of precisely detecting a phase difference between a data signal and a clock signal. According to some implementations, the present disclosure is directed to a receiver that includes an analog front end configured to receive a data input/output signal, and amplify the data input/output signal, to generate a processing signal, a time interleaved analog-to-digital converter (TI ADC) configured to sample the processing signal based on a plurality of clock signals and generate a plurality of digital data signals, a Mueller-Muller phase detector configured to receive the digital data signals from the time interleaved analog-to-digital converter and drive at least one of a plurality of calculators based on a transition between two digital data signals received sequentially among the digital data signals, a monitoring circuit configured to receive the digital data signals from the time interleaved analog-to-digital converter, receive a multi-level signal transmitted from a transmitter, and generate a monitoring output signal based on the digital data signals and the multi-level signal, and a control logic configured to receive a monitoring output signal output from the monitoring circuit and generate a plurality of calculator selection signals for driving the calculators based on the monitoring output signal. According to some implementations, the present disclosure is directed to a phase detection device that includes a plurality of calculators configured to output a plurality of sampling control signals corresponding to transitions of two adjacent digital data signals and controlling sampling timing for sampling the signals, a monitoring circuit configured to obtain the digital data signal, receive a multi-level signal having one of N signal levels (N is a positive number) from a transmitter, and generate a monitoring output signal using the digital data signal and the multi-level signal, a control logic configured to compare the monitoring output signal with a first reference value and generate a plurality of calculator selection signals that drive the calculators, and a plurality of switches configured to transfer a driving voltage from a voltage source to the calculators based on the calculator selection signals. According to some implementations, the present disclosure is directed to a phase detection method that includes computing a bit error rate based on a multi-level signal having one of N (N is a positive number) signal levels received from a transmitter and a digital data signal obtained from a time interleaved analog-to-digital converter, comparing the computed bit error rate with a first reference value and generating a plurality of calculator selection signals for turning on or off a plurality of switches respectively connected between a plurality of calculators and a voltage source based on a compared result value thereof, and supplying the calculator selection signals to the switches and the multiplexers that receive sampling control signals output from the calculators. BRIEF DESCRIPTION OF THE DRAWINGS Example implementations will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings. FIG. 1 illustrates a block diagram of an example of a memory system according to some implementations.FIG. 2 illustrates a block diagram showing an example of a memory device according to some implementations.FIGS. 3 and 4 illustrate block diagrams showing examples of a transmitter and a receiver included in each of a memory controller and a memory device according to some implementations.FIG. 5 illustrates a block diagram showing an example of a data transmitting/receiving system according to some implementations.FIG. 6 illustrates a graph showing an example of a processing signal according to some implementations.FIG. 7 illustrates a circuit diagram of an example of a time interleaved analog-to-digital converter according to some implementations.FIG. 8