EP-4738763-A2 - ANTI-HACKING MECHANISMS FOR FLASH MEMORY DEVICE

Abstract

Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

Inventors

• TRAN, HIEU VAN
• TIWARI, Vipin
• DO, NHAN

Assignees

• Silicon Storage Technology Inc.

Dates

Publication Date

20260506

Application Date

20180922

Claims (4)

1. A flash memory system, comprising: an array comprising a plurality of flash memory cells organized into rows and columns; an analog mixed signal fault detection circuit; a logic fault detection circuit; and an address fault detection circuit; wherein access to the array is enabled if none of the analog mixed signal fault detection circuit, the logic fault detection circuit, and the address fault detection circuit detects a fault and access to the array is disabled if at least one of the analog mixed signal fault detection circuit, the logic fault detection circuit, or the address fault detection circuit detects a fault.
2. The flash memory system of claim 1, wherein the plurality of flash memory cells are split gate flash memory cells.
3. A flash memory system, comprising: an array comprising a plurality of flash memory cells organized into rows and columns; and power balanced latch sense amplifier circuitry comprising: a data read block for sourcing current during a read operation to a selected flash memory cell corresponding to a received address and contained within the plurality of flash memory cells; a reference read block coupled to a holding capacitor; a differential amplifier for comparing current drawn by the data read block and the reference read block during the read operation to generate an output indicative of a value stored in the selected flash memory cell; and a balancing power circuit for maintaining a minimum voltage in the read circuit block in response to any data pattern.
4. The flash memory system of claim 3, wherein the plurality of flash memory cells are split gate flash memory cells.

Description

This application claims the benefit of U.S. Patent Application No. 15/784,025, filed on October 13, 2017. TECHNICAL FIELD A multitude of mechanisms are disclosed for enhancing security and preventing hacking of a flash memory device. BACKGROUND OF THE INVENTION Non-volatile memory cells are well known in the art. One prior art non-volatile split gate memory cell 10, which contains five terminals, is shown in Figure 1. Memory cell 10 comprises semiconductor substrate 12 of a first conductivity type, such as P type. Substrate 12 has a surface on which there is formed a first region 14 (also known as the source line SL) of a second conductivity type, such as N type. A second region 16 (also known as the drain line) also of N type is formed on the surface of substrate 12. Between the first region 14 and the second region 16 is channel region 18. Bit line BL 20 is connected to the second region 16. Word line WL 22 is positioned above a first portion of the channel region 18 and is insulated therefrom. Word line 22 has little or no overlap with the second region 16. Floating gate FG 24 is over another portion of channel region 18. Floating gate 24 is insulated therefrom, and is adjacent to word line 22. Floating gate 24 is also adjacent to the first region 14. Floating gate 24 may overlap the first region 14 to provide coupling from the first region 14 into floating gate 24. Coupling gate CG (also known as control gate) 26 is over floating gate 24 and is insulated therefrom. Erase gate EG 28 is over the first region 14 and is adjacent to floating gate 24 and coupling gate 26 and is insulated therefrom. The top corner of floating gate 24 may point toward the inside corner of the T-shaped erase gate 28 to enhance erase efficiency. Erase gate 28 is also insulated from the first region 14. Memory cell 10 is more particularly described in U.S. Patent No. 7,868,375, whose disclosure is incorporated herein by reference in its entirety. One exemplary operation for erase and program of prior art non-volatile memory cell 10 is as follows. Memory cell 10 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on erase gate 28 with other terminals equal to zero volts. Electrons tunnel from floating gate 24 into erase gate 28 causing floating gate 24 to be positively charged, turning on the cell 10 in a read condition. The resulting cell erased state is known as '1' state. Memory cell 10 is programmed, through a source side hot electron programming mechanism, by applying a high voltage on coupling gate 26, a high voltage on source line 14, a medium voltage on erase gate 28, and a programming current on bit line 20. A portion of electrons flowing across the gap between word line 22 and floating gate 24 acquire enough energy to inject into floating gate 24 causing the floating gate 24 to be negatively charged, turning off the cell 10 in a read condition. The resulting cell programmed state is known as '0' state. Memory cell 10 is read in a Current Sensing Mode as following: A bias voltage is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias or zero voltage is applied on erase gate 28, and a ground is applied on source line 14. There exists a cell current flowing from bit line 20 to source line 14 for an erased state and there is insignificant or zero cell current flow from the bit line 20 to the source line 14 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Current Sensing Mode, in which bit line 20 is grounded and a bias voltage is applied on source line 24. In this mode the current reverses the direction from source line 14 to bitline 20. Memory cell 10 alternatively can be read in a Voltage Sensing Mode as following: A bias current (to ground) is applied on bit line 20, a bias voltage is applied on word line 22, a bias voltage is applied on coupling gate 26, a bias voltage is applied on erase gate 28, and a bias voltage is applied on source line 14. There exists a cell output voltage (significantly >0V) on bit line 20 for an erased state and there is insignificant or close to zero output voltage on bit line 20 for a programmed state. Alternatively, memory cell 10 can be read in a Reverse Voltage Sensing Mode, in which bit line 20 is biased at a bias voltage and a bias current (to ground) is applied on source line 14. In this mode, memory cell 10 output voltage is on the source line 14 instead of on the bit line 20. In the prior art, various combinations of positive or zero voltages were applied to word line 22, coupling gate 26, and floating gate 24 to perform read, program, and erase operations In response to the read, erase or program command, the logic circuit 451 (in Figure 4) causes the various voltages to be supplied in a timely and least disturb manner to the various portions of both the selected memory cell 10 and the unselected memory cells 10. For the selected and unselected memory cell