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EP-4739022-A1 - SEMICONDUCTOR DEVICE INCLUDING ACTIVE PORTION AND BIT LINE

EP4739022A1EP 4739022 A1EP4739022 A1EP 4739022A1EP-4739022-A1

Abstract

Provided is a semiconductor device including: a first active portion (AF1); an isolation region (STI) on a side surface of the first active portion (AF1); and a bit line (BL) connected to the first active portion (AF1), wherein the first active portion (AF1) includes a first region (AP1) in contact with the isolation region (STI) and a second region (AP2) extending upwardly from the first region (AP1), wherein the second region (AP2) is spaced apart from the isolation region (STI), and wherein the bit line (BL) includes: a line portion (LP) extending in a horizontal direction (Y); and a contact portion (CP) below the line portion (LP), wherein the contact portion (CP) is connected to the second region (AP2) of the first active portion (AFI).

Inventors

  • HAN, EUNSHOO
  • PARK, CHANHOON
  • Jeon, Hayoung

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260506
Application Date
20251022

Claims (15)

  1. A semiconductor device comprising: a first active portion (AF1); an isolation region (STI) on a side surface of the first active portion (AF1); and a bit line (BL) connected to the first active portion (AF1), wherein the first active portion (AF1) comprises a first region (AP1) in contact with the isolation region (STI) and a second region (AP2) extending upwardly from the first region (AP1), wherein the second region (AP2) is spaced apart from the isolation region (STI), and wherein the bit line (BL) comprises: a line portion (LP) extending in a horizontal direction (Y); and a contact portion (CP) below the line portion (LP), wherein the contact portion (CP) is connected to the second region (AP2) of the first active portion (AF1).
  2. The semiconductor device of claim 1, further comprising: an insulating spacer structure (SP) comprising a contact spacer (SP_C) and a line spacer (SP_L), wherein the contact spacer (SP_C) is on a side surface of the second region (AP2) of the first active portion (AF1) and a side surface of the contact portion (CP), and wherein the line spacer is on a side surface of the line portion (LP).
  3. The semiconductor device of claim 2, wherein a width of the contact spacer (SP_C) is greater than a width of the line spacer (SP_L).
  4. The semiconductor device of claim 2 or 3, wherein the isolation region (STI) is in contact with a side surface of the first region (AP1) of the first active portion (AF1), and wherein the contact spacer (SP_C) is in contact with the side surface of the second region (AP2) of the first active portion (AF1) and the side surface of the contact portion (CP).
  5. The semiconductor device of any one of claims 1 to 4, wherein the contact portion (CP) extends from the line portion (LP).
  6. The semiconductor device any one of claims 1 to 5, wherein the line portion (LP) comprises a first conductive layer (12a), a second conductive layer (12b), and a third conductive layer (12c), wherein the first conductive layer (12a), the second conductive layer (12b), and the third conductive layer (12c) are sequentially stacked, wherein the contact portion (CP) extends from the first conductive layer (12a) of the line portion (LP), and wherein the first conductive layer (12a) comprises doped polysilicon.
  7. The semiconductor device of any one of claims 1 to 6, wherein the side surface of the first active portion (AF1) has a bent portion (APB) between a side surface (AP1S) of the first region (AP1) and a side surface (AP2S) of the second region (AP2).
  8. The semiconductor device of any one of claims 2 to 7, further comprising: a second active portion (AF2) adjacent to the first active portion (AF1) and spaced apart from the first active portion (AF1) by the isolation region (STI), wherein an upper surface (AF2_U) of the second active portion (AF2) is at a first height level (L3), wherein an upper surface (AF1_U) of the second region (AP2) of the first active portion (AF1) is at a second height level (L2), wherein a region between a side surface (AP1S) of the first region (AP1) of the first active portion and a side surface (AP2S) of the second region (AP2) of the first active portion (AF1) is at a third height level (L1), and wherein the second height level (L2) is at a lower level than the first height level (L3).
  9. The semiconductor device of claim 8, wherein the isolation region (STI) is between the first region (AP1) of the first active portion (AF1) and the second active portion (AF2), and wherein the isolation region (STI) extends from a portion between the first region (AP1) of the first active portion (AF1) and the second active portion (AF2) to a point between the contact spacer (SP_C) and the second active portion (AF2).
  10. The semiconductor device of claim 8 or 9, wherein in the first active portion (AF1), a vertical thickness of the second region (AP2) is greater than a width of the second region (AP2).
  11. The semiconductor device of any one of claims 8 to 10, further comprising: a contact structure (CNT) on the second active portion (AF2); and a data storage structure (DS) on the contact structure (CNT), wherein a lower surface of the contact structure (CNT) is at a higher level than the upper surface (AF1_U) of the first active portion (AF1).
  12. The semiconductor device of any one of claims 8 to 11, further comprising: a gate structure (GS), wherein the gate structure (GS) comprises: a gate electrode (GE); a gate capping pattern (GC) on the gate electrode (GE); and a gate dielectric layer (Gox) on a side surface and a lower surface of the gate electrode (GE), and wherein the first active portion (AF1) and the second active portion (AF2) are spaced apart from each other by the gate structure (GS).
  13. The semiconductor device of claim 12, further comprising: an insulating pattern (8), wherein the insulating pattern (8) is between the gate capping pattern of the gate structure (GS) and the first active portion (AF1), and wherein the contact portion (CP) of the bit line (BL) comprises a portion contacting the first active portion (AF1) and a portion contacting the insulating pattern (8).
  14. The semiconductor device of any one of claims 1 to 13, wherein an upper surface (AF1_U) of the first active portion (AF1) is upwardly convex.
  15. The semiconductor device of claim 14, wherein the contact portion (CP) of the bit line (BL) is in contact with the upper surface (AF1_U) of the first active portion (AF1).

Description

BACKGROUND The present disclosure relates to a semiconductor device including an active portion and a bit line and a method for forming the semiconductor device. Research is being conducted to reduce the size of elements constituting a semiconductor device and to improve the performance thereof. For example, in a DRAM, research is being conducted to reliably and stably form reduced-size elements. SUMMARY Provided is a semiconductor device for increasing a degree of integration. Further provided is a semiconductor device for improving reliability. Further provided is a method for manufacturing a semiconductor device that can increase a degree of integration and improve reliability. According to an aspect of the disclosure, a semiconductor device includes: a first active portion; an isolation region on a side surface of the first active portion; and a bit line connected to the first active portion, wherein the first active portion includes a first region in contact with the isolation region and a second region extending upwardly from the first region, wherein the second region is spaced apart from the isolation region, and wherein the bit line includes: a line portion extending in a first horizontal direction; and a contact portion below the line portion, wherein the contact portion is connected to the second region of the first active portion. According to an aspect of the disclosure, a semiconductor device includes: a first active portion; a second active portion adjacent to the first active portion; an isolation region between the first active portion and the second active portion; a bit line connected to the first active portion; a contact structure connected to the second active portion; and a data storage structure connected to the contact structure, wherein the first active portion includes an upper surface, wherein the upper surface of the first active portion is upwardly convex, and wherein the bit line includes: a contact portion contacting the upper surface of the first active portion; and a line portion on the contact portion, the line portion extending in a first horizontal direction. According to an aspect of the disclosure, a semiconductor device includes: active regions; an isolation region between the active regions; gate structures extending across the active regions and into the isolation region; and bit lines connected to the active regions, wherein each of the active regions includes a first active portion and a second active portion, wherein the first active portion and the second active portion of each respective active region of the active regions are spaced apart from each other by a gate structure crossing the respective active region from among the gate structures, wherein the active regions include a first active region, wherein the bit lines include a first bit line connected to the first active portion of the first active region, wherein the first active portion of the first active region includes: a first region including a side surface in contact with the isolation region; and a second region extending upwardly from the first region, the second region being spaced apart from the isolation region, and wherein the first bit line includes: a line portion extending in a first horizontal direction; and a contact portion below the line portion and connected to the second region of the first active portion. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects and features of certain embodiments of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: FIG. 1A is a plan view illustrating a semiconductor device according to one or more embodiments of the present disclosure;FIG. 1B is a plan view illustrating some elements of FIG. 1A;FIG. 2A is a cross-sectional view illustrating a region taken along line I-I' of FIG. 1A;FIG. 2B is a partial enlarged view illustrating a region indicated by "A" in FIG. 2A.FIG. 3 is a cross-sectional view illustrating a region taken along line II-II' of FIG. 1A;FIGS. 4A and 4B are drawings illustrating a semiconductor device according to one or more embodiments of the present disclosure;FIGS. 5A and 5B are drawings illustrating a semiconductor device according to one or more embodiments of the present disclosure;FIGS. 6A and 6B are drawings illustrating a semiconductor device according to one or more embodiments of the present disclosure; andFIGS. 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 are drawings illustrating an example of a method for forming a semiconductor device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION Hereinafter, terms such as "upper," "intermediate," and "lower" may be replaced with other terms, such as "first," "second," and "third," to describe elements of the specification. Although the terms "first," "second," and "third" may be used to describe various elements, the elements are not limited b