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EP-4739023-A1 - SEMICONDUCTOR DEVICE INCLUDING MULTIPLE DIES

EP4739023A1EP 4739023 A1EP4739023 A1EP 4739023A1EP-4739023-A1

Abstract

A semiconductor device may include a plurality of dies (10) stacked in a vertical direction (Z), wherein each of the plurality of dies (10) includes: a first substrate (110); a cell capacitor (CAP) on the first substrate (110); a cell transistor (CTR) on the cell capacitor (CAP); a second substrate (210), wherein a vertical level of the second substrate (210) is higher than a vertical level of the cell transistor (CTR); a peripheral circuit transistor (PTR) on the second substrate (210); and a through via (12) passing through the first substrate (110) and the second substrate (210) in the vertical direction (Z).

Inventors

  • KANG, PILKYU
  • PARK, JAEWHA
  • MOON, KWANGJIN
  • KIM, EUNMI
  • LEE, CHANMI

Assignees

  • Samsung Electronics Co., Ltd.

Dates

Publication Date
20260506
Application Date
20251027

Claims (15)

  1. A semiconductor device comprising: a plurality of dies (10) stacked in a vertical direction (Z), wherein each of the plurality of dies (10) comprises: a first substrate (110); a cell capacitor (CAP) on the first substrate (110); a cell transistor (CTR) on the cell capacitor (CAP); a second substrate (210), wherein a vertical level of the second substrate (210) is higher than a vertical level of the cell transistor (CTR); a peripheral circuit transistor (PTR) on the second substrate (210); and a through via (12) passing through the first substrate (110) and the second substrate (210) in the vertical direction (Z).
  2. The semiconductor device of claim 1, wherein each of the plurality of dies (10) further comprises: a wiring pattern (WP) that at least partially vertically overlaps with the through via (12), wherein a vertical level of the wiring pattern (WP) is higher than a vertical level of the peripheral circuit transistor (PTR); a front-side pad (14P) on an upper surface of the wiring pattern (WP) ; and a backside pad (16P) on a lower surface of the through via (12).
  3. The semiconductor device of claim 2, wherein the plurality of dies (10) comprise a first die (C1) and a second die (C2) on the first die (C3), and the through via (12) of the first die (C1) and the through via (12) of the second die (C2) are electrically connected to each other, and the second die (C2) is on an upper surface of the first die (C1) such that the backside pad of the second die (C2) is attached to the front-side pad (14P) of the first die (C1).
  4. The semiconductor device of claim 2 or 3, wherein each of the plurality of dies (10) further comprises: a front-side insulation layer (14I) on the upper surface of the wiring pattern (WP), and an upper surface of the front-side insulation layer (14I) is coplanar with an upper surface of the front-side pad (14P); and a backside insulation layer (16I) on a lower surface of the first substrate (110), and a lower surface of the backside insulation layer (16I) is coplanar with a lower surface of the backside pad (16P), the plurality of dies (10) comprise a first die (C1) and a second die (C2) on the first die (C1), and the upper surface of the front-side insulation layer (14I) of the first die (C1) contacts a lower surface of the backside insulation layer (16I) of the second die (C2).
  5. The semiconductor device of any one of claims 2 to 4, wherein each of the plurality of dies (10) further comprises a through via contact (220) extending in the vertical direction (Z) in a via hole (210H) passing through the second substrate (210) and electrically connecting the peripheral circuit transistor (PTR) to the cell transistor (CTR).
  6. The semiconductor device of any one of claims 1 to 5, wherein the cell transistor (CTR) comprises: a channel layer (AP) extending in the vertical direction (Z); a word line (WL) on one sidewall of the channel layer (AP) and extending in a first horizontal direction; and a bit line (BL) on an upper surface of the channel layer (AP) and extending in a second horizontal direction intersecting with the first horizontal direction.
  7. The semiconductor device of claim 6, wherein the channel layer (AP) comprises silicon, germanium, silicon germanium, or an oxide semiconductor.
  8. The semiconductor device of any one of claims 1 to 7, wherein each of the plurality of dies (10) further comprises a through via insulation layer (12I) surrounding a sidewall of the through via (12), the first substrate (110) comprises a first through via hole (H1) passing through the first substrate (110), the second substrate (210) comprises a second through via hole (H2) passing through the second substrate (210), the second through via hole (H2) vertically overlapping with the first through via hole (H1).
  9. The semiconductor device of claim 8, wherein the through via (12) is vertically overlapping with the first through via hole (H1) and the second through via hole (H2).
  10. The semiconductor device of claim 8 or 9, wherein the through via (12) comprises an upper surface, wherein a vertical level of the upper surface of the through via (12) is higher than a vertical level of an upper surface of the second substrate (210), and the through via (12) comprises a lower surface, wherein a vertical level of the lower surface of the through via (12) is lower than a vertical level of a lower surface of the first substrate (110).
  11. The semiconductor device of any one of claims 8 to 10, wherein the through via insulation layer (12I) comprises an upper surface, wherein a vertical level of the upper surface of the through via insulation layer (12I) is higher than a vertical level of an upper surface of the second substrate (210), and the through via insulation layer (12I) comprises a lower surface, wherein a vertical level of the lower surface of the through via insulation layer (12I) is lower than a vertical level of a lower surface of the first substrate (110).
  12. The semiconductor device of any one of claims 8 to 11, wherein a first portion of the through via insulation layer (12I) is between the sidewall of the through via (12) and an inner wall of the first through via hole (H1), a second portion of the through via insulation layer (12I) is between the sidewall of the through via (12) and an inner wall of the second through via hole (H2).
  13. The semiconductor device of claim 12, wherein the through via (12) is electrically insulated from the first substrate (110) or the second substrate (210).
  14. The semiconductor device of any one of claims 8 to 13, wherein each of the plurality of dies (10) further comprises: a buried insulation layer (134) between the first substrate (110) and the second substrate (210) and on the cell transistor (CTR).
  15. The semiconductor device of claim 14, wherein the through via insulation layer (12I) is on an entire sidewall of the through via (12), and at least a portion of a sidewall of the through via insulation layer (12I) contacts the buried insulation layer (134).

Description

BACKGROUND The disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a stack structure of a plurality of dies. To enhance the performance and storage capacity of semiconductor devices, semiconductor devices having a structure where a plurality of semiconductor dies are stacked are being used widely. As semiconductor devices are down-scaled, the size of dynamic random access memory (DRAM) devices is also reduced, and in DRAM devices having a 1T-1C structure where one capacitor is connected to one transistor, there is a problem where a leakage current occurring through a channel region increases progressively. Therefore, there is a need for vertical channel transistors including a channel layer extending in a vertical direction for decreasing a leakage current. SUMMARY One or more embodiments provide a semiconductor device having a structure where a plurality of semiconductor dies including a vertical channel transistor having good electrical performance are stacked. According to an aspect of the disclosure, a semiconductor device may include a plurality of dies stacked in a vertical direction, wherein each of the plurality of dies includes: a first substrate; a cell capacitor on the first substrate; a cell transistor on the cell capacitor; a second substrate, wherein a vertical level of the second substrate is higher than a vertical level of the cell transistor; a peripheral circuit transistor on the second substrate; and a through via passing through the first substrate and the second substrate in the vertical direction. According to an aspect of the disclosure, a semiconductor device may include: a first die; and a second die on the first die, wherein each of the first die and the second die includes: a first substrate; a cell capacitor on the first substrate; a cell transistor on the cell capacitor; a second substrate, wherein a vertical level of the second substrate is higher than a vertical level of the cell transistor; a peripheral circuit transistor on the second substrate; a through via passing through the first substrate and the second substrate in a vertical direction; a wiring pattern that at least partially vertically overlaps with the through via, wherein a vertical level of the wiring pattern is higher than a vertical level of the peripheral circuit transistor; a front-side pad (14P) on an upper surface of the wiring pattern; and a backside pad on a lower surface of the through via. According to an aspect of the disclosure, a semiconductor device may include: a first substrate including a first through via hole; a cell capacitor on the first substrate; a cell transistor on the cell capacitor; a second substrate, wherein a vertical level of the second substrate is higher than a vertical level of the cell transistor, and the second substrate includes a second through via hole that vertically overlaps with the first through via hole; a peripheral circuit transistor on the second substrate; a through via contact extending in a vertical direction in a via hole passing through the second substrate, and the through via contact electrically connects the peripheral circuit transistor to the cell transistor; a through via passing through the first through via hole and the second through via hole in the vertical direction; a through via insulation layer on a sidewall of the through via; a wiring pattern at least partially vertically overlapping with the through via, wherein a vertical level of the wiring pattern is higher than a vertical level of the peripheral circuit transistor; a front-side pad on an upper surface of the wiring pattern; a front-side insulation layer on the upper surface of the wiring pattern, and an upper surface of the front-side insulation layer being coplanar with an upper surface of the front-side pad; a backside pad on a lower surface of the through via; and a backside insulation layer on a lower surface of the first substrate, and a lower surface of the backside insulation layer being coplanar with a lower surface of the backside pad. BRIEF DESCRIPTION OF DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 is a schematic diagram illustrating a semiconductor device according to embodiments;FIG. 2 is a perspective view schematically illustrating each semiconductor die of FIG. 1;FIG. 3 is a cross-sectional view illustrating a region A of FIG. 1;FIG. 4 is a cross-sectional view schematically illustrating a cell array region of FIG. 2;FIG. 5 is a cross-sectional view schematically illustrating a cell array region according to embodiments; andFIGS. 6 to 8, 9A, 9B, 10 to 21, 22A, and 22B are schematic diagrams illustrating a method of manufacturing a semiconductor device, according to embodiments. DETAILED DESCRIPTION It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" a